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| author | Andreas Hansson <andreas.hansson@arm.com> | 2015-05-05 03:22:24 -0400 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2015-05-05 03:22:24 -0400 |
| commit | 0ebbf3f9512609c089257158abd14b9366b72b52 (patch) | |
| tree | f4cf1da2c6b2cb619319fe03653556206916f8c4 /tests/configs/simple-timing.py | |
| parent | 33e3e370f217badf6f309e601c16f09eb3080f22 (diff) | |
| download | gem5-0ebbf3f9512609c089257158abd14b9366b72b52.tar.xz | |
mem: Add missing stats update for uncacheable MSHRs
This patch adds a missing counter update for the uncacheable
accesses. By updating this counter we also get a meaningful average
latency for uncacheable accesses (previously inf).
Diffstat (limited to 'tests/configs/simple-timing.py')
0 files changed, 0 insertions, 0 deletions