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author | Kevin Lim <ktlim@umich.edu> | 2007-04-22 14:39:39 -0400 |
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committer | Kevin Lim <ktlim@umich.edu> | 2007-04-22 14:39:39 -0400 |
commit | d1f9414e111b4b5e6d0f60ca64a415a47765e9e0 (patch) | |
tree | 1bb6a06cffe906558ebf86873236be9e643d88a2 /tests/configs/simple-timing.py | |
parent | 25e92383c839f6d69f933f614fd3f9acef907075 (diff) | |
download | gem5-d1f9414e111b4b5e6d0f60ca64a415a47765e9e0.tar.xz |
Update configs to set the CPU clock properly.
--HG--
extra : convert_revision : 62fec666f987e9a9a441e319458908483cd2c5ff
Diffstat (limited to 'tests/configs/simple-timing.py')
-rw-r--r-- | tests/configs/simple-timing.py | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/tests/configs/simple-timing.py b/tests/configs/simple-timing.py index d7d505a5a..6c4b8232f 100644 --- a/tests/configs/simple-timing.py +++ b/tests/configs/simple-timing.py @@ -1,4 +1,4 @@ -# Copyright (c) 2006 The Regents of The University of Michigan +# Copyright (c) 2006-2007 The Regents of The University of Michigan # All rights reserved. # # Redistribution and use in source and binary forms, with or without @@ -44,5 +44,6 @@ system = System(cpu = cpu, membus = Bus()) system.physmem.port = system.membus.port cpu.connectMemPorts(system.membus) +cpu.clock = '2GHz' root = Root(system = system) |