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authorAndreas Hansson <andreas.hansson@arm.com>2012-10-30 07:44:08 -0400
committerAndreas Hansson <andreas.hansson@arm.com>2012-10-30 07:44:08 -0400
commit9cbe1cb653428a2298644579ddf82c46272683d4 (patch)
treef02848bbbdfbc6c083e134969389cdc6a671e613 /tests/configs/simple-timing.py
parent30f5bf5f23672a5946f12616bb1a592d84e04645 (diff)
downloadgem5-9cbe1cb653428a2298644579ddf82c46272683d4.tar.xz
config: Unify caches used in regressions and adjust L2 MSHRs
This patch unified the L1 and L2 caches used throughout the regressions instead of declaring different, but very similar, configurations in the different scripts. The patch also changes the default L2 configuration to match what it used to be for the fs and se scripts (until the last patch that updated the regressions to also make use of the cache config). The MSHRs and targets per MSHR are now set to a more realistic default of 20 and 12, respectively. As a result of both the aforementioned changes, many of the regression stats are changed. A follow-on patch will bump the stats.
Diffstat (limited to 'tests/configs/simple-timing.py')
-rw-r--r--tests/configs/simple-timing.py20
1 files changed, 5 insertions, 15 deletions
diff --git a/tests/configs/simple-timing.py b/tests/configs/simple-timing.py
index beeadced9..5a851ba25 100644
--- a/tests/configs/simple-timing.py
+++ b/tests/configs/simple-timing.py
@@ -28,23 +28,13 @@
import m5
from m5.objects import *
-
-class MyCache(BaseCache):
- assoc = 2
- block_size = 64
- hit_latency = 2
- response_latency = 2
- mshrs = 10
- tgts_per_mshr = 5
-
-class MyL1Cache(MyCache):
- is_top_level = True
+m5.util.addToPath('../configs/common')
+from Caches import *
cpu = TimingSimpleCPU(cpu_id=0)
-cpu.addTwoLevelCacheHierarchy(MyL1Cache(size = '128kB'),
- MyL1Cache(size = '256kB'),
- MyCache(size = '2MB', hit_latency= 20,
- response_latency = 20))
+cpu.addTwoLevelCacheHierarchy(L1Cache(size = '128kB'),
+ L1Cache(size = '256kB'),
+ L2Cache(size = '2MB'))
system = System(cpu = cpu,
physmem = SimpleMemory(),
membus = CoherentBus())