summaryrefslogtreecommitdiff
path: root/tests/configs/simple-timing.py
diff options
context:
space:
mode:
authorAkash Bagdia <akash.bagdia@arm.com>2013-06-27 05:49:49 -0400
committerAkash Bagdia <akash.bagdia@arm.com>2013-06-27 05:49:49 -0400
commit076d04a653f5a4252c6c16e010ad0d7bf36c1674 (patch)
tree1be09e01ab286960ae6fcd5d767bfb0e10270ec2 /tests/configs/simple-timing.py
parent4459b305251109ff147d72142452e25c74542ebd (diff)
downloadgem5-076d04a653f5a4252c6c16e010ad0d7bf36c1674.tar.xz
config: Add a system clock command-line option
This patch adds a 'sys_clock' command-line option and use it to assign clocks to the system during instantiation. As part of this change, the default clock in the System class is removed and whenever a system is instantiated a system clock value must be set. A default value is provided for the command-line option. The configs and tests are updated accordingly.
Diffstat (limited to 'tests/configs/simple-timing.py')
-rw-r--r--tests/configs/simple-timing.py1
1 files changed, 1 insertions, 0 deletions
diff --git a/tests/configs/simple-timing.py b/tests/configs/simple-timing.py
index b366f01e5..046ee96dd 100644
--- a/tests/configs/simple-timing.py
+++ b/tests/configs/simple-timing.py
@@ -39,6 +39,7 @@ system = System(cpu = cpu,
physmem = SimpleMemory(),
membus = CoherentBus(),
mem_mode = "timing")
+system.clock = '1GHz'
system.system_port = system.membus.slave
system.physmem.port = system.membus.master
# create the interrupt controller