tests: Always specify memory mode in every test system.

Previous to this change we didn't always set the memory mode which worked as
long as we never attempted to switch CPUs or checked that a CPU was in a
memory system with the correct mode. Future changes will make CPUs verify
that they're operating in the correct mode and thus we need to always set it.

1 files changed, 2 insertions, 1 deletions

diff --git a/tests/configs/simple-timing.py b/tests/configs/simple-timing.py
index 5a851ba25..b366f01e5 100644
--- a/tests/configs/simple-timing.py
+++ b/tests/configs/simple-timing.py
@@ -37,7 +37,8 @@ cpu.addTwoLevelCacheHierarchy(L1Cache(size = '128kB'),
                               L2Cache(size = '2MB'))
 system = System(cpu = cpu,
                 physmem = SimpleMemory(),
-                membus = CoherentBus())
+                membus = CoherentBus(),
+                mem_mode = "timing")
 system.system_port = system.membus.slave
 system.physmem.port = system.membus.master
 # create the interrupt controller