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authorAndreas Sandberg <Andreas.Sandberg@ARM.com>2013-02-15 17:40:08 -0500
committerAndreas Sandberg <Andreas.Sandberg@ARM.com>2013-02-15 17:40:08 -0500
commite5dca84c3f15c63fe19195510d342458402a0716 (patch)
tree6ec39ac06144a2a4113c6dd12d75014cf1c92a62 /tests/configs/switcheroo.py
parente9f66dceac5ce2665001f9f74222964ef0aef74b (diff)
downloadgem5-e5dca84c3f15c63fe19195510d342458402a0716.tar.xz
config: Move CPU handover logic to m5.switchCpus()
CPU switching consists of the following steps: 1. Drain the system 2. Switch out old CPUs (cpu.switchOut()) 3. Change the system timing mode to the mode the new CPUs require 4. Flush caches if switching to hardware virtualization 5. Inform new CPUs of the handover (cpu.takeOverFrom()) 6. Resume the system m5.switchCpus() previously only did step 2 & 5. Since information about the new processors' memory system requirements is now exposed, do all of the steps above. This patch adds automatic memory system switching and flush (if needed) to switchCpus(). Additionally, it adds optional draining to switchCpus(). This has the following implications: * changeToTiming and changeToAtomic are no longer needed, so they have been removed. * changeMemoryMode is only used internally, so it is has been renamed to be private. * switchCpus requires a reference to the system containing the CPUs as its first parameter. WARNING: This changeset breaks compatibility with existing configuration scripts since it changes the signature of m5.switchCpus().
Diffstat (limited to 'tests/configs/switcheroo.py')
-rw-r--r--tests/configs/switcheroo.py12
1 files changed, 3 insertions, 9 deletions
diff --git a/tests/configs/switcheroo.py b/tests/configs/switcheroo.py
index dadf8db03..4b2dd9a69 100644
--- a/tests/configs/switcheroo.py
+++ b/tests/configs/switcheroo.py
@@ -40,12 +40,6 @@ from m5.objects import *
m5.util.addToPath('../configs/common')
from Caches import *
-def _memMode(cclass):
- if cclass == AtomicSimpleCPU:
- return "atomic", m5.objects.params.atomic
- else:
- return "timing", m5.objects.params.timing
-
class Sequential:
"""Sequential CPU switcher.
@@ -104,7 +98,7 @@ def run_test(root, switcher=None, freq=1000):
current_cpu = switcher.first()
system = root.system
- system.mem_mode = _memMode(type(current_cpu))[0]
+ system.mem_mode = type(current_cpu).memory_mode()
# instantiate configuration
m5.instantiate()
@@ -122,9 +116,9 @@ def run_test(root, switcher=None, freq=1000):
print "Switching CPUs..."
print "Next CPU: %s" % type(next_cpu)
m5.drain(system)
- system.setMemoryMode(_memMode(type(next_cpu))[1])
if current_cpu != next_cpu:
- m5.switchCpus([ (current_cpu, next_cpu) ])
+ m5.switchCpus(system, [ (current_cpu, next_cpu) ],
+ do_drain=False)
else:
print "Source CPU and destination CPU are the same, skipping..."
m5.resume(system)