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| author | Akash Bagdia <akash.bagdia@arm.com> | 2013-06-27 05:49:49 -0400 |
|---|---|---|
| committer | Akash Bagdia <akash.bagdia@arm.com> | 2013-06-27 05:49:49 -0400 |
| commit | 7eccb1b779cb6458ed78ba73f2fdabe94fa805b3 (patch) | |
| tree | a47dc043defd5ff0afad3bdf103bc1a147dc0091 /tests/configs/tgen-simple-mem.py | |
| parent | f821c5472b5e524053846bd57b83c81238be159f (diff) | |
| download | gem5-7eccb1b779cb6458ed78ba73f2fdabe94fa805b3.tar.xz | |
config: Remove redundant explicit setting of default clocks
This patch removes the explicit setting of the clock period for
certain instances of CoherentBus, NonCoherentBus and IOCache where the
specified clock is same as the default value of the system clock. As
all the values used are the defaults, there are no performance
changes. There are similar cases where the toL2Bus is set to use the
parent CPU clock which is already the default behaviour.
The main motivation for these simplifications is to ease the
introduction of clock domains.
Diffstat (limited to 'tests/configs/tgen-simple-mem.py')
| -rw-r--r-- | tests/configs/tgen-simple-mem.py | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/tests/configs/tgen-simple-mem.py b/tests/configs/tgen-simple-mem.py index d402e557c..200834ec3 100644 --- a/tests/configs/tgen-simple-mem.py +++ b/tests/configs/tgen-simple-mem.py @@ -49,7 +49,7 @@ cpu = TrafficGen(config_file = "tests/quick/se/70.tgen/tgen-simple-mem.cfg") # system simulated system = System(cpu = cpu, physmem = SimpleMemory(), - membus = NoncoherentBus(clock="1GHz", width = 16)) + membus = NoncoherentBus(width = 16)) # add a communication monitor, and also trace all the packets system.monitor = CommMonitor(trace_file = "monitor.ptrc.gz") |