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author | Akash Bagdia <akash.bagdia@arm.com> | 2013-06-27 05:49:49 -0400 |
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committer | Akash Bagdia <akash.bagdia@arm.com> | 2013-06-27 05:49:49 -0400 |
commit | 076d04a653f5a4252c6c16e010ad0d7bf36c1674 (patch) | |
tree | 1be09e01ab286960ae6fcd5d767bfb0e10270ec2 /tests/configs/tgen-simple-mem.py | |
parent | 4459b305251109ff147d72142452e25c74542ebd (diff) | |
download | gem5-076d04a653f5a4252c6c16e010ad0d7bf36c1674.tar.xz |
config: Add a system clock command-line option
This patch adds a 'sys_clock' command-line option and use it to assign
clocks to the system during instantiation.
As part of this change, the default clock in the System class is
removed and whenever a system is instantiated a system clock value
must be set. A default value is provided for the command-line option.
The configs and tests are updated accordingly.
Diffstat (limited to 'tests/configs/tgen-simple-mem.py')
-rw-r--r-- | tests/configs/tgen-simple-mem.py | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/tests/configs/tgen-simple-mem.py b/tests/configs/tgen-simple-mem.py index 200834ec3..b93165f50 100644 --- a/tests/configs/tgen-simple-mem.py +++ b/tests/configs/tgen-simple-mem.py @@ -50,6 +50,7 @@ cpu = TrafficGen(config_file = "tests/quick/se/70.tgen/tgen-simple-mem.cfg") # system simulated system = System(cpu = cpu, physmem = SimpleMemory(), membus = NoncoherentBus(width = 16)) +system.clock = '1GHz' # add a communication monitor, and also trace all the packets system.monitor = CommMonitor(trace_file = "monitor.ptrc.gz") |