Mem: Use cycles to express cache-related latencies

This patch changes the cache-related latencies from an absolute time
expressed in Ticks, to a number of cycles that can be scaled with the
clock period of the caches. Ultimately this patch serves to enable
future work that involves dynamic frequency scaling. As an immediate
benefit it also makes it more convenient to specify cache performance
without implicitly assuming a specific CPU core operating frequency.

The stat blocked_cycles that actually counter in ticks is now updated
to count in cycles.

As the timing is now rounded to the clock edges of the cache, there
are some regressions that change. Plenty of them have very minor
changes, whereas some regressions with a short run-time are perturbed
quite significantly. A follow-on patch updates all the statistics for
the regressions.

1 files changed, 9 insertions, 9 deletions

diff --git a/tests/configs/tsunami-o3-dual.py b/tests/configs/tsunami-o3-dual.py
index a40c44c9b..5ba14753d 100644
--- a/tests/configs/tsunami-o3-dual.py
+++ b/tests/configs/tsunami-o3-dual.py
@@ -37,8 +37,8 @@ import FSConfig
 # ====================
 
 class L1(BaseCache):
-    hit_latency = '1ns'
-    response_latency = '1ns'
+    hit_latency = 2
+    response_latency = 2
     block_size = 64
     mshrs = 4
     tgts_per_mshr = 20
@@ -50,8 +50,8 @@ class L1(BaseCache):
 
 class L2(BaseCache):
     block_size = 64
-    hit_latency = '10ns'
-    response_latency = '10ns'
+    hit_latency = 20
+    response_latency = 20
     mshrs = 92
     tgts_per_mshr = 16
     write_buffers = 8
@@ -62,8 +62,8 @@ class L2(BaseCache):
 class IOCache(BaseCache):
     assoc = 8
     block_size = 64
-    hit_latency = '50ns'
-    response_latency = '50ns'
+    hit_latency = 50
+    response_latency = 50
     mshrs = 20
     size = '1kB'
     tgts_per_mshr = 12
@@ -78,14 +78,14 @@ system = FSConfig.makeLinuxAlphaSystem('timing')
 
 system.cpu = cpus
 #create the l1/l2 bus
-system.toL2Bus = CoherentBus()
-system.iocache = IOCache()
+system.toL2Bus = CoherentBus(clock = '2GHz')
+system.iocache = IOCache(clock = '1GHz')
 system.iocache.cpu_side = system.iobus.master
 system.iocache.mem_side = system.membus.slave
 
 
 #connect up the l2 cache
-system.l2c = L2(size='4MB', assoc=8)
+system.l2c = L2(clock = '2GHz', size='4MB', assoc=8)
 system.l2c.cpu_side = system.toL2Bus.master
 system.l2c.mem_side = system.membus.slave