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authorAndreas Hansson <andreas.hansson@arm.com>2012-10-26 06:42:42 -0400
committerAndreas Hansson <andreas.hansson@arm.com>2012-10-26 06:42:42 -0400
commit651de2d9af8ac628b69b40812ff036231da40ae3 (patch)
treeabb19706695f402c23370963ecd20166f657681d /tests/configs/tsunami-simple-atomic-dual.py
parentb387d8e2136b6eccf590e5223096dce6830a66ec (diff)
downloadgem5-651de2d9af8ac628b69b40812ff036231da40ae3.tar.xz
config: Fix the cache class naming in regression scripts
This patch unifies the naming of the default L1 and L2 caches in the regression configs to be in line with what is used in the se and fs scripts.
Diffstat (limited to 'tests/configs/tsunami-simple-atomic-dual.py')
-rw-r--r--tests/configs/tsunami-simple-atomic-dual.py6
1 files changed, 3 insertions, 3 deletions
diff --git a/tests/configs/tsunami-simple-atomic-dual.py b/tests/configs/tsunami-simple-atomic-dual.py
index 1f63ff7a8..b91d56cec 100644
--- a/tests/configs/tsunami-simple-atomic-dual.py
+++ b/tests/configs/tsunami-simple-atomic-dual.py
@@ -45,14 +45,14 @@ system.cpu = cpus
system.toL2Bus = CoherentBus(clock = '2GHz')
#connect up the l2 cache
-system.l2c = L2(clock = '2GHz', size='4MB', assoc=8)
+system.l2c = L2Cache(clock = '2GHz', size='4MB', assoc=8)
system.l2c.cpu_side = system.toL2Bus.master
system.l2c.mem_side = system.membus.slave
#connect up the cpu and l1s
for c in cpus:
- c.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1),
- L1(size = '32kB', assoc = 4))
+ c.addPrivateSplitL1Caches(L1Cache(size = '32kB', assoc = 1),
+ L1Cache(size = '32kB', assoc = 4))
# create the interrupt controller
c.createInterruptController()
# connect cpu level-1 caches to shared level-2 cache