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authorSteve Reinhardt <stever@eecs.umich.edu>2006-08-18 00:16:23 -0400
committerSteve Reinhardt <stever@eecs.umich.edu>2006-08-18 00:16:23 -0400
commit4e3164617ad709cb6d4b0f8fbbdfd596f4d6f236 (patch)
tree9d1e42532d876c646fb91d18b0f70803bb62fd9f /tests/configs/tsunami-simple-timing.py
parent2b70b74c9bc575005a26fd727be26e11ac6db032 (diff)
downloadgem5-4e3164617ad709cb6d4b0f8fbbdfd596f4d6f236.tar.xz
Add caches in, fix cpu.mem param
--HG-- extra : convert_revision : 486283d83786807c72bb4601e4b9613b55d8802c
Diffstat (limited to 'tests/configs/tsunami-simple-timing.py')
-rw-r--r--tests/configs/tsunami-simple-timing.py1
1 files changed, 1 insertions, 0 deletions
diff --git a/tests/configs/tsunami-simple-timing.py b/tests/configs/tsunami-simple-timing.py
index 5dba7508d..b3fc9d105 100644
--- a/tests/configs/tsunami-simple-timing.py
+++ b/tests/configs/tsunami-simple-timing.py
@@ -35,5 +35,6 @@ cpu = TimingSimpleCPU()
system = FSConfig.makeLinuxAlphaSystem('timing')
system.cpu = cpu
cpu.connectMemPorts(system.membus)
+cpu.mem = system.physmem
root = Root(clock = '2GHz', system = system)