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author | Ali Saidi <saidi@eecs.umich.edu> | 2007-05-13 04:48:42 -0400 |
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committer | Ali Saidi <saidi@eecs.umich.edu> | 2007-05-13 04:48:42 -0400 |
commit | 404a91265efbf1a039fe1e19a8c1d8ff86a904b1 (patch) | |
tree | 3d4c5f1d882fa0c521acf273e8d00fd2a3abdd46 /tests/configs/tsunami-simple-timing.py | |
parent | 376cff64bd3ac5bafd8fa566674964fd4836790c (diff) | |
parent | 011db5c8515804145202373440bad26fa21b30a7 (diff) | |
download | gem5-404a91265efbf1a039fe1e19a8c1d8ff86a904b1.tar.xz |
Merge zizzer.eecs.umich.edu:/z/m5/Bitkeeper/newmem
into zizzer.eecs.umich.edu:/tmp/newmem
--HG--
extra : convert_revision : 162876cb1ad96ca7ca6a2e0f549c98b29e5a8d2d
Diffstat (limited to 'tests/configs/tsunami-simple-timing.py')
-rw-r--r-- | tests/configs/tsunami-simple-timing.py | 44 |
1 files changed, 42 insertions, 2 deletions
diff --git a/tests/configs/tsunami-simple-timing.py b/tests/configs/tsunami-simple-timing.py index 9f532e3ae..999bde087 100644 --- a/tests/configs/tsunami-simple-timing.py +++ b/tests/configs/tsunami-simple-timing.py @@ -31,10 +31,50 @@ from m5.objects import * m5.AddToPath('../configs/common') import FSConfig + +# -------------------- +# Base L1 Cache +# ==================== + +class L1(BaseCache): + latency = '1ns' + block_size = 64 + mshrs = 4 + tgts_per_mshr = 8 + protocol = CoherenceProtocol(protocol='moesi') + +# ---------------------- +# Base L2 Cache +# ---------------------- + +class L2(BaseCache): + block_size = 64 + latency = '10ns' + mshrs = 92 + tgts_per_mshr = 16 + write_buffers = 8 + +#cpu cpu = TimingSimpleCPU(cpu_id=0) +#the system system = FSConfig.makeLinuxAlphaSystem('timing') + system.cpu = cpu -cpu.connectMemPorts(system.membus) +#create the l1/l2 bus +system.toL2Bus = Bus() + +#connect up the l2 cache +system.l2c = L2(size='4MB', assoc=8) +system.l2c.cpu_side = system.toL2Bus.port +system.l2c.mem_side = system.membus.port + +#connect up the cpu and l1s +cpu.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1), + L1(size = '32kB', assoc = 4)) +# connect cpu level-1 caches to shared level-2 cache +cpu.connectMemPorts(system.toL2Bus) +cpu.clock = '2GHz' root = Root(system=system) -m5.ticks.setGlobalFrequency('2GHz') +m5.ticks.setGlobalFrequency('1THz') + |