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authorAli Saidi <saidi@eecs.umich.edu>2007-08-10 16:14:02 -0400
committerAli Saidi <saidi@eecs.umich.edu>2007-08-10 16:14:02 -0400
commit9493501fdb087c82111d8692995474f2e8f3f390 (patch)
treee9c87ab5f27c44399bc91628d60f7c4fa7565627 /tests/configs/tsunami-simple-timing.py
parent06a9f58c68b621f082d39299bdb01f59ef68ef0e (diff)
downloadgem5-9493501fdb087c82111d8692995474f2e8f3f390.tar.xz
Regression: Add an I/O Cache to the full system regressions that have a cache.
--HG-- extra : convert_revision : 8ba96e21be2f602eed8258d410038dbe998ef176
Diffstat (limited to 'tests/configs/tsunami-simple-timing.py')
-rw-r--r--tests/configs/tsunami-simple-timing.py19
1 files changed, 19 insertions, 0 deletions
diff --git a/tests/configs/tsunami-simple-timing.py b/tests/configs/tsunami-simple-timing.py
index 3f18c6848..96cd27111 100644
--- a/tests/configs/tsunami-simple-timing.py
+++ b/tests/configs/tsunami-simple-timing.py
@@ -53,6 +53,19 @@ class L2(BaseCache):
tgts_per_mshr = 16
write_buffers = 8
+# ---------------------
+# I/O Cache
+# ---------------------
+class IOCache(BaseCache):
+ assoc = 8
+ block_size = 64
+ latency = '50ns'
+ mshrs = 20
+ size = '1kB'
+ tgts_per_mshr = 12
+ mem_side_filter_ranges=[AddrRange(0, Addr.max)]
+ cpu_side_filter_ranges=[AddrRange(0x8000000000, Addr.max)]
+
#cpu
cpu = TimingSimpleCPU(cpu_id=0)
#the system
@@ -61,6 +74,12 @@ system = FSConfig.makeLinuxAlphaSystem('timing')
system.cpu = cpu
#create the l1/l2 bus
system.toL2Bus = Bus()
+system.bridge.filter_ranges_a=[AddrRange(0, Addr.max)]
+system.bridge.filter_ranges_b=[AddrRange(0, size='8GB')]
+system.iocache = IOCache()
+system.iocache.cpu_side = system.iobus.port
+system.iocache.mem_side = system.membus.port
+
#connect up the l2 cache
system.l2c = L2(size='4MB', assoc=8)