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| author | Andreas Hansson <andreas.hansson@arm.com> | 2013-08-19 03:52:27 -0400 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2013-08-19 03:52:27 -0400 |
| commit | a8480fe1c34db25ae8acb5f79d571bc924e0daeb (patch) | |
| tree | c8c792eefae54e9c1599b371720dc5f8e9c9440a /tests/configs/twosys-tsunami-simple-atomic.py | |
| parent | d5593f3c75c9d005b89788647a9383e791c9c2a2 (diff) | |
| download | gem5-a8480fe1c34db25ae8acb5f79d571bc924e0daeb.tar.xz | |
config: Move the memory instantiation outside FSConfig
This patch moves the instantiation of the memory controller outside
FSConfig and instead relies on the mem_ranges to pass the information
to the caller (e.g. fs.py or one of the regression scripts). The main
motivation for this change is to expose the structural composition of
the memory system and allow more tuning and configuration without
adding a large number of options to the makeSystem functions.
The patch updates the relevant example scripts to maintain the current
functionality. As the order that ports are connected to the memory bus
changes (in certain regresisons), some bus stats are shuffled
around. For example, what used to be layer 0 is now layer 1.
Going forward, options will be added to support the addition of
multi-channel memory controllers.
Diffstat (limited to 'tests/configs/twosys-tsunami-simple-atomic.py')
| -rw-r--r-- | tests/configs/twosys-tsunami-simple-atomic.py | 12 |
1 files changed, 9 insertions, 3 deletions
diff --git a/tests/configs/twosys-tsunami-simple-atomic.py b/tests/configs/twosys-tsunami-simple-atomic.py index 22c6686ae..b69e35517 100644 --- a/tests/configs/twosys-tsunami-simple-atomic.py +++ b/tests/configs/twosys-tsunami-simple-atomic.py @@ -32,8 +32,8 @@ m5.util.addToPath('../configs/common') from FSConfig import * from Benchmarks import * -test_sys = makeLinuxAlphaSystem('atomic', SimpleMemory, - SysConfig('netperf-stream-client.rcS')) +test_sys = makeLinuxAlphaSystem('atomic', + SysConfig('netperf-stream-client.rcS')) # Create the system clock domain test_sys.clk_domain = SrcClockDomain(clock = '1GHz') @@ -57,7 +57,10 @@ test_sys.iobridge = Bridge(delay='50ns', ranges = test_sys.mem_ranges) test_sys.iobridge.slave = test_sys.iobus.master test_sys.iobridge.master = test_sys.membus.slave -drive_sys = makeLinuxAlphaSystem('atomic', SimpleMemory, +test_sys.physmem = SimpleMemory(range = test_sys.mem_ranges[0]) +test_sys.physmem.port = test_sys.membus.master + +drive_sys = makeLinuxAlphaSystem('atomic', SysConfig('netperf-server.rcS')) # Create the system clock domain drive_sys.clk_domain = SrcClockDomain(clock = '1GHz') @@ -77,6 +80,9 @@ drive_sys.iobridge = Bridge(delay='50ns', ranges = drive_sys.mem_ranges) drive_sys.iobridge.slave = drive_sys.iobus.master drive_sys.iobridge.master = drive_sys.membus.slave +drive_sys.physmem = SimpleMemory(range = drive_sys.mem_ranges[0]) +drive_sys.physmem.port = drive_sys.membus.master + root = makeDualRoot(True, test_sys, drive_sys, "ethertrace") maxtick = 199999999 |