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| author | Andreas Hansson <andreas.hansson@arm.com> | 2015-07-03 10:14:39 -0400 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2015-07-03 10:14:39 -0400 |
| commit | 893533a1264bb369b47f74493adf30ce22829f34 (patch) | |
| tree | 07c750519f5ac1b972be47a0ca6f68ee517d9f07 /tests/configs/x86_generic.py | |
| parent | a262908acc0a641700a03fcea89c48133f0467cd (diff) | |
| download | gem5-893533a1264bb369b47f74493adf30ce22829f34.tar.xz | |
mem: Allow read-only caches and check compliance
This patch adds a parameter to the BaseCache to enable a read-only
cache, for example for the instruction cache, or table-walker cache
(not for x86). A number of checks are put in place in the code to
ensure a read-only cache does not end up with dirty data.
A follow-on patch adds suitable read requests to allow a read-only
cache to explicitly ask for clean data.
Diffstat (limited to 'tests/configs/x86_generic.py')
| -rw-r--r-- | tests/configs/x86_generic.py | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/tests/configs/x86_generic.py b/tests/configs/x86_generic.py index 5dc8702ba..ad3ea31bf 100644 --- a/tests/configs/x86_generic.py +++ b/tests/configs/x86_generic.py @@ -81,8 +81,8 @@ class LinuxX86FSSystem(LinuxX86SystemBuilder, LinuxX86SystemBuilder.__init__(self) def create_caches_private(self, cpu): - cpu.addPrivateSplitL1Caches(L1Cache(size='32kB', assoc=1), - L1Cache(size='32kB', assoc=4), + cpu.addPrivateSplitL1Caches(L1_ICache(size='32kB', assoc=1), + L1_DCache(size='32kB', assoc=4), PageTableWalkerCache(), PageTableWalkerCache()) @@ -100,8 +100,8 @@ class LinuxX86FSSystemUniprocessor(LinuxX86SystemBuilder, LinuxX86SystemBuilder.__init__(self) def create_caches_private(self, cpu): - cpu.addTwoLevelCacheHierarchy(L1Cache(size='32kB', assoc=1), - L1Cache(size='32kB', assoc=4), + cpu.addTwoLevelCacheHierarchy(L1_ICache(size='32kB', assoc=1), + L1_DCache(size='32kB', assoc=4), L2Cache(size='4MB', assoc=8), PageTableWalkerCache(), PageTableWalkerCache()) |