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| author | Nikos Nikoleris <nikos.nikoleris@arm.com> | 2018-02-05 09:45:20 +0000 |
|---|---|---|
| committer | Nikos Nikoleris <nikos.nikoleris@arm.com> | 2018-05-31 17:45:23 +0000 |
| commit | 51056cec69a72931a319e7be9370ea63f18e1aa3 (patch) | |
| tree | 9ba8760c4b488879674cfa715ac0b5fff1f4b36c /tests/configs | |
| parent | 7d990bd25b478d906442ea63e1de6b381b51817b (diff) | |
| download | gem5-51056cec69a72931a319e7be9370ea63f18e1aa3.tar.xz | |
mem-cache: Add a non-coherent cache
The class re-uses the existing MSHR and write queue. At the moment
every single access is handled by the cache, even uncacheable
accesses, and nothing is forwarded.
This is a modified version of a changeset put together by Andreas
Hansson <andreas.hansson@arm.com>
Change-Id: I41f7f9c2b8c7fa5ec23712a4446e8adb1c9a336a
Reviewed-on: https://gem5-review.googlesource.com/8291
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Diffstat (limited to 'tests/configs')
| -rw-r--r-- | tests/configs/base_config.py | 15 |
1 files changed, 13 insertions, 2 deletions
diff --git a/tests/configs/base_config.py b/tests/configs/base_config.py index 732d537ea..e09963314 100644 --- a/tests/configs/base_config.py +++ b/tests/configs/base_config.py @@ -1,4 +1,4 @@ -# Copyright (c) 2012-2013, 2017 ARM Limited +# Copyright (c) 2012-2013, 2017-2018 ARM Limited # All rights reserved. # # The license below extends only to copyright in the software and shall @@ -278,8 +278,19 @@ class BaseFSSystem(BaseSystem): # the physmem name to avoid bumping all the reference stats system.physmem = [self.mem_class(range = r) for r in system.mem_ranges] + system.llc = [NoncoherentCache(addr_ranges = [r], + size = '4kB', + assoc = 2, + mshrs = 128, + tag_latency = 10, + data_latency = 10, + sequential_access = True, + response_latency = 20, + tgts_per_mshr = 8) + for r in system.mem_ranges] for i in xrange(len(system.physmem)): - system.physmem[i].port = system.membus.master + system.physmem[i].port = system.llc[i].mem_side + system.llc[i].cpu_side = system.membus.master # create the iocache, which by default runs at the system clock system.iocache = IOCache(addr_ranges=system.mem_ranges) |