SimpleDRAM: A basic SimpleDRAM regression

--HG--
rename : tests/configs/tgen-simple-mem.py => tests/configs/tgen-simple-dram.py
rename : tests/quick/se/70.tgen/tgen-simple-mem.cfg => tests/quick/se/70.tgen/tgen-simple-dram.cfg
rename : tests/quick/se/70.tgen/tgen-simple-mem.trc => tests/quick/se/70.tgen/tgen-simple-dram.trc

1 files changed, 67 insertions, 0 deletions

diff --git a/tests/configs/tgen-simple-dram.py b/tests/configs/tgen-simple-dram.py
new file mode 100644
index 000000000..76762cdc8
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+++ b/tests/configs/tgen-simple-dram.py
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+# Copyright (c) 2012 ARM Limited
+# All rights reserved.
+#
+# The license below extends only to copyright in the software and shall
+# not be construed as granting a license to any other intellectual
+# property including but not limited to intellectual property relating
+# to a hardware implementation of the functionality of the software
+# licensed hereunder.  You may use the software subject to the license
+# terms below provided that you ensure that this notice is replicated
+# unmodified and in its entirety in all distributions of the software,
+# modified or unmodified, in source code or in binary form.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Andreas Hansson
+
+import m5
+from m5.objects import *
+
+# even if this is only a traffic generator, call it cpu to make sure
+# the scripts are happy
+cpu = TrafficGen(config_file = "tests/quick/se/70.tgen/tgen-simple-dram.cfg")
+
+# system simulated
+system = System(cpu = cpu, physmem = SimpleDRAM(),
+                membus = NoncoherentBus(clock="1GHz", width = 16))
+
+# add a communication monitor
+system.monitor = CommMonitor()
+
+# connect the traffic generator to the bus via a communication monitor
+system.cpu.port = system.monitor.slave
+system.monitor.master = system.membus.slave
+
+# connect the system port even if it is not used in this example
+system.system_port = system.membus.slave
+
+# connect memory to the membus
+system.physmem.port = system.membus.master
+
+# -----------------------
+# run simulation
+# -----------------------
+
+root = Root(full_system = False, system = system)
+root.system.mem_mode = 'timing'