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| author | Nilay Vaish <nilay@cs.wisc.edu> | 2014-02-24 20:50:05 -0600 |
|---|---|---|
| committer | Nilay Vaish <nilay@cs.wisc.edu> | 2014-02-24 20:50:05 -0600 |
| commit | 8504b079b8e1c5bc4c14fa42ba224fe182ca43df (patch) | |
| tree | 2ee42015d22e46e4d732117ef83081035cc68b8b /tests/configs | |
| parent | 3b404fb1a0e21aedcd4597d1683fd251bb9302fa (diff) | |
| download | gem5-8504b079b8e1c5bc4c14fa42ba224fe182ca43df.tar.xz | |
ruby: correct errors in changeset 4eec7bdde5b0
Couple of errors were discovered in 4eec7bdde5b0 which necessitated this patch.
Firstly, we create interrupt controllers in the se mode, but no piobus was
being created. RubyPort, which earlier used to ignore range changes now
forwards those to the piobus. The lack of piobus resulted in segmentation
fault. This patch creates a piobus even in se mode. It is not created only
when some tester is running. Secondly, I had missed out on modifying port
connections for other coherence protocols.
Diffstat (limited to 'tests/configs')
| -rw-r--r-- | tests/configs/simple-timing-ruby.py | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/tests/configs/simple-timing-ruby.py b/tests/configs/simple-timing-ruby.py index df8fdf2be..d3f4ad2ae 100644 --- a/tests/configs/simple-timing-ruby.py +++ b/tests/configs/simple-timing-ruby.py @@ -79,8 +79,8 @@ system.cpu.clk_domain = SrcClockDomain(clock = '2GHz', voltage_domain = system.voltage_domain) system.mem_ranges = AddrRange('256MB') - -Ruby.create_system(options, system) +system.piobus = NoncoherentBus() +Ruby.create_system(options, system, system.piobus) # Create a separate clock for Ruby system.ruby.clk_domain = SrcClockDomain(clock = options.ruby_clock, |