ruby: interface with classic memory controller

This patch is the final in the series.  The whole series and this patch in
particular were written with the aim of interfacing ruby's directory controller
with the memory controller in the classic memory system.  This is being done
since ruby's memory controller has not being kept up to date with the changes
going on in DRAMs.  Classic's memory controller is more up to date and
supports multiple different types of DRAM.  This also brings classic and
ruby ever more close.  The patch also changes ruby's memory controller to
expose the same interface.

5 files changed, 4 insertions, 9 deletions

diff --git a/tests/configs/memtest-ruby.py b/tests/configs/memtest-ruby.py
index badd64e63..f71370c5e 100644
--- a/tests/configs/memtest-ruby.py
+++ b/tests/configs/memtest-ruby.py
@@ -80,7 +80,6 @@ options.num_cpus = nb_cores
 # system simulated
 system = System(cpu = cpus,
                 funcmem = SimpleMemory(in_addr_map = False),
-                physmem = SimpleMemory(null = True),
                 funcbus = NoncoherentXBar())
 # Dummy voltage domain for all our clock domains
 system.voltage_domain = VoltageDomain()
diff --git a/tests/configs/pc-simple-timing-ruby.py b/tests/configs/pc-simple-timing-ruby.py
index 633a19e2f..782cda60d 100644
--- a/tests/configs/pc-simple-timing-ruby.py
+++ b/tests/configs/pc-simple-timing-ruby.py
@@ -91,8 +91,5 @@ for (i, cpu) in enumerate(system.cpu):
     cpu.interrupts.int_master = system.ruby._cpu_ports[i].slave
     cpu.interrupts.int_slave = system.ruby._cpu_ports[i].master
 
-system.physmem = [SimpleMemory(range = r, null = True)
-                  for r in system.mem_ranges]
-
 root = Root(full_system = True, system = system)
 m5.ticks.setGlobalFrequency('1THz')
diff --git a/tests/configs/rubytest-ruby.py b/tests/configs/rubytest-ruby.py
index cbb578938..22334efb4 100644
--- a/tests/configs/rubytest-ruby.py
+++ b/tests/configs/rubytest-ruby.py
@@ -80,7 +80,7 @@ tester = RubyTester(check_flush = check_flush, checks_to_complete = 100,
 
 # We set the testers as cpu for ruby to find the correct clock domains
 # for the L1 Objects.
-system = System(cpu = tester, physmem = SimpleMemory(null = True))
+system = System(cpu = tester)
 
 # Dummy voltage domain for all our clock domains
 system.voltage_domain = VoltageDomain(voltage = options.sys_voltage)
diff --git a/tests/configs/simple-timing-mp-ruby.py b/tests/configs/simple-timing-mp-ruby.py
index da7733acb..263b330fb 100644
--- a/tests/configs/simple-timing-mp-ruby.py
+++ b/tests/configs/simple-timing-mp-ruby.py
@@ -71,8 +71,7 @@ cpus = [ TimingSimpleCPU(cpu_id=i) for i in xrange(nb_cores) ]
 options.num_cpus = nb_cores
 
 # system simulated
-system = System(cpu = cpus, physmem = SimpleMemory(),
-                clk_domain = SrcClockDomain(clock = '1GHz'))
+system = System(cpu = cpus, clk_domain = SrcClockDomain(clock = '1GHz'))
 
 # Create a seperate clock domain for components that should run at
 # CPUs frequency
diff --git a/tests/configs/simple-timing-ruby.py b/tests/configs/simple-timing-ruby.py
index 3ce6266c1..b9fb650e5 100644
--- a/tests/configs/simple-timing-ruby.py
+++ b/tests/configs/simple-timing-ruby.py
@@ -65,9 +65,9 @@ options.l3_assoc=2
 
 # this is a uniprocessor only test
 options.num_cpus = 1
-
 cpu = TimingSimpleCPU(cpu_id=0)
-system = System(cpu = cpu, physmem = SimpleMemory(null = True))
+system = System(cpu = cpu)
+
 # Dummy voltage domain for all our clock domains
 system.voltage_domain = VoltageDomain(voltage = options.sys_voltage)
 system.clk_domain = SrcClockDomain(clock = '1GHz',