summaryrefslogtreecommitdiff
path: root/tests/configs
diff options
context:
space:
mode:
authorAndreas Hansson <andreas.hansson@arm.com>2013-05-30 12:54:14 -0400
committerAndreas Hansson <andreas.hansson@arm.com>2013-05-30 12:54:14 -0400
commit3bc4ecdcb4785a976a1c3fd463bf7052b8415d8b (patch)
tree309adeb0381c44177d4992a79a5590ba90f61a7e /tests/configs
parent83d99aebb1dcbe015e752fd74e9cd5c6b5ea0380 (diff)
downloadgem5-3bc4ecdcb4785a976a1c3fd463bf7052b8415d8b.tar.xz
mem: More descriptive DRAM config names
This patch changes the class names of the variuos DRAM configurations to better reflect what memory they are based on. The speed and interface width is now part of the name, and also the alias that is used to select them on the command line. Some minor changes are done to the actual parameters, to better reflect the named configurations. As a result of these changes the regressions change slightly and the stats will be bumped in a separate patch.
Diffstat (limited to 'tests/configs')
-rw-r--r--tests/configs/alpha_generic.py2
-rw-r--r--tests/configs/arm_generic.py2
-rw-r--r--tests/configs/inorder-timing.py2
-rw-r--r--tests/configs/o3-timing-checker.py2
-rw-r--r--tests/configs/o3-timing-mp.py2
-rw-r--r--tests/configs/o3-timing.py2
-rw-r--r--tests/configs/pc-simple-timing-ruby.py2
-rw-r--r--tests/configs/t1000-simple-atomic.py2
-rw-r--r--tests/configs/tgen-simple-dram.py2
-rw-r--r--tests/configs/twosys-tsunami-simple-atomic.py4
-rw-r--r--tests/configs/x86_generic.py2
11 files changed, 12 insertions, 12 deletions
diff --git a/tests/configs/alpha_generic.py b/tests/configs/alpha_generic.py
index 5060eae39..f7a4166be 100644
--- a/tests/configs/alpha_generic.py
+++ b/tests/configs/alpha_generic.py
@@ -59,7 +59,7 @@ class LinuxAlphaSystemBuilder(object):
pass
def create_system(self):
- system = FSConfig.makeLinuxAlphaSystem(self.mem_mode, SimpleDDR3)
+ system = FSConfig.makeLinuxAlphaSystem(self.mem_mode, DDR3_1600_x64)
self.init_system(system)
return system
diff --git a/tests/configs/arm_generic.py b/tests/configs/arm_generic.py
index e6c56041b..0cf170a9b 100644
--- a/tests/configs/arm_generic.py
+++ b/tests/configs/arm_generic.py
@@ -61,7 +61,7 @@ class LinuxArmSystemBuilder(object):
def create_system(self):
system = FSConfig.makeArmSystem(self.mem_mode,
self.machine_type,
- SimpleDDR3,
+ DDR3_1600_x64,
None, False)
# We typically want the simulator to panic if the kernel
diff --git a/tests/configs/inorder-timing.py b/tests/configs/inorder-timing.py
index 77c4f3d18..b19014328 100644
--- a/tests/configs/inorder-timing.py
+++ b/tests/configs/inorder-timing.py
@@ -39,7 +39,7 @@ cpu.addTwoLevelCacheHierarchy(L1Cache(size = '128kB'),
cpu.clock = '2GHz'
system = System(cpu = cpu,
- physmem = SimpleDDR3(),
+ physmem = DDR3_1600_x64(),
membus = CoherentBus(),
mem_mode = "timing")
system.system_port = system.membus.slave
diff --git a/tests/configs/o3-timing-checker.py b/tests/configs/o3-timing-checker.py
index cd15cf66b..84fcb0f83 100644
--- a/tests/configs/o3-timing-checker.py
+++ b/tests/configs/o3-timing-checker.py
@@ -52,7 +52,7 @@ cpu.addTwoLevelCacheHierarchy(L1Cache(size = '128kB'),
cpu.clock = '2GHz'
system = System(cpu = cpu,
- physmem = SimpleDDR3(),
+ physmem = DDR3_1600_x64(),
membus = CoherentBus(),
mem_mode = "timing")
system.system_port = system.membus.slave
diff --git a/tests/configs/o3-timing-mp.py b/tests/configs/o3-timing-mp.py
index 59f91a392..b7401f629 100644
--- a/tests/configs/o3-timing-mp.py
+++ b/tests/configs/o3-timing-mp.py
@@ -36,7 +36,7 @@ cpus = [ DerivO3CPU(cpu_id=i) for i in xrange(nb_cores) ]
# system simulated
system = System(cpu = cpus,
- physmem = SimpleDDR3(),
+ physmem = DDR3_1600_x64(),
membus = CoherentBus(),
mem_mode = "timing")
diff --git a/tests/configs/o3-timing.py b/tests/configs/o3-timing.py
index 8c3c9abe7..a370beef4 100644
--- a/tests/configs/o3-timing.py
+++ b/tests/configs/o3-timing.py
@@ -41,7 +41,7 @@ cpu.addTwoLevelCacheHierarchy(L1Cache(size = '128kB'),
cpu.clock = '2GHz'
system = System(cpu = cpu,
- physmem = SimpleDDR3(),
+ physmem = DDR3_1600_x64(),
membus = CoherentBus(),
mem_mode = "timing")
system.system_port = system.membus.slave
diff --git a/tests/configs/pc-simple-timing-ruby.py b/tests/configs/pc-simple-timing-ruby.py
index 6413133c2..f17083fe4 100644
--- a/tests/configs/pc-simple-timing-ruby.py
+++ b/tests/configs/pc-simple-timing-ruby.py
@@ -55,7 +55,7 @@ options.num_cpus = 2
#the system
mdesc = SysConfig(disk = 'linux-x86.img')
-system = FSConfig.makeLinuxX86System('timing', SimpleDDR3, options.num_cpus,
+system = FSConfig.makeLinuxX86System('timing', DDR3_1600_x64, options.num_cpus,
mdesc=mdesc, Ruby=True)
system.kernel = FSConfig.binary('x86_64-vmlinux-2.6.22.9.smp')
system.cpu = [TimingSimpleCPU(cpu_id=i) for i in xrange(options.num_cpus)]
diff --git a/tests/configs/t1000-simple-atomic.py b/tests/configs/t1000-simple-atomic.py
index 3ba1afecd..7f04751b8 100644
--- a/tests/configs/t1000-simple-atomic.py
+++ b/tests/configs/t1000-simple-atomic.py
@@ -32,7 +32,7 @@ m5.util.addToPath('../configs/common')
import FSConfig
cpu = AtomicSimpleCPU(cpu_id=0)
-system = FSConfig.makeSparcSystem('atomic', SimpleDDR3)
+system = FSConfig.makeSparcSystem('atomic', SimpleMemory)
system.cpu = cpu
# create the interrupt controller
cpu.createInterruptController()
diff --git a/tests/configs/tgen-simple-dram.py b/tests/configs/tgen-simple-dram.py
index 19eb15933..407852682 100644
--- a/tests/configs/tgen-simple-dram.py
+++ b/tests/configs/tgen-simple-dram.py
@@ -48,7 +48,7 @@ require_sim_object("CommMonitor")
cpu = TrafficGen(config_file = "tests/quick/se/70.tgen/tgen-simple-dram.cfg")
# system simulated
-system = System(cpu = cpu, physmem = SimpleDDR3(),
+system = System(cpu = cpu, physmem = DDR3_1600_x64(),
membus = NoncoherentBus(clock="1GHz", width = 16))
# add a communication monitor
diff --git a/tests/configs/twosys-tsunami-simple-atomic.py b/tests/configs/twosys-tsunami-simple-atomic.py
index 89d497008..484236fae 100644
--- a/tests/configs/twosys-tsunami-simple-atomic.py
+++ b/tests/configs/twosys-tsunami-simple-atomic.py
@@ -32,7 +32,7 @@ m5.util.addToPath('../configs/common')
from FSConfig import *
from Benchmarks import *
-test_sys = makeLinuxAlphaSystem('atomic', SimpleDDR3,
+test_sys = makeLinuxAlphaSystem('atomic', SimpleMemory,
SysConfig('netperf-stream-client.rcS'))
test_sys.cpu = AtomicSimpleCPU(cpu_id=0)
# create the interrupt controller
@@ -46,7 +46,7 @@ test_sys.iobridge = Bridge(delay='50ns', ranges = test_sys.mem_ranges)
test_sys.iobridge.slave = test_sys.iobus.master
test_sys.iobridge.master = test_sys.membus.slave
-drive_sys = makeLinuxAlphaSystem('atomic', SimpleDDR3,
+drive_sys = makeLinuxAlphaSystem('atomic', SimpleMemory,
SysConfig('netperf-server.rcS'))
drive_sys.cpu = AtomicSimpleCPU(cpu_id=0)
# create the interrupt controller
diff --git a/tests/configs/x86_generic.py b/tests/configs/x86_generic.py
index 9a499cc60..be28ba687 100644
--- a/tests/configs/x86_generic.py
+++ b/tests/configs/x86_generic.py
@@ -58,7 +58,7 @@ class LinuxX86SystemBuilder(object):
def create_system(self):
mdesc = SysConfig(disk = 'linux-x86.img')
system = FSConfig.makeLinuxX86System(self.mem_mode,
- SimpleDDR3,
+ DDR3_1600_x64,
numCPUs=self.num_cpus,
mdesc=mdesc)
system.kernel = FSConfig.binary('x86_64-vmlinux-2.6.22.9')