mem: use single BadAddr responder per system.

Previously there was one per bus, which caused some coherence problems
when more than one decided to respond.  Now there is just one on
the main memory bus.  The default bus responder on all other buses
is now the downstream cache's cpu_side port.  Caches no longer need
to do address range filtering; instead, we just have a simple flag
to prevent snoops from propagating to the I/O bus.

6 files changed, 12 insertions, 12 deletions

diff --git a/tests/configs/tsunami-o3-dual.py b/tests/configs/tsunami-o3-dual.py
index 5dbfa5a8b..3044f5433 100644
--- a/tests/configs/tsunami-o3-dual.py
+++ b/tests/configs/tsunami-o3-dual.py
@@ -63,8 +63,8 @@ class IOCache(BaseCache):
     mshrs = 20
     size = '1kB'
     tgts_per_mshr = 12
-    mem_side_filter_ranges=[AddrRange(0, Addr.max)]
-    cpu_side_filter_ranges=[AddrRange(0x8000000000, Addr.max)]
+    addr_range=AddrRange(0, size='8GB')
+    forward_snoops = False
 
 #cpu
 cpus = [ DerivO3CPU(cpu_id=i) for i in xrange(2) ]
diff --git a/tests/configs/tsunami-o3.py b/tests/configs/tsunami-o3.py
index ee60ea8ae..34fa235bd 100644
--- a/tests/configs/tsunami-o3.py
+++ b/tests/configs/tsunami-o3.py
@@ -63,8 +63,8 @@ class IOCache(BaseCache):
     mshrs = 20
     size = '1kB'
     tgts_per_mshr = 12
-    mem_side_filter_ranges=[AddrRange(0, Addr.max)]
-    cpu_side_filter_ranges=[AddrRange(0x8000000000, Addr.max)]
+    addr_range=AddrRange(0, size='8GB')
+    forward_snoops = False
 
 #cpu
 cpu = DerivO3CPU(cpu_id=0)
diff --git a/tests/configs/tsunami-simple-atomic-dual.py b/tests/configs/tsunami-simple-atomic-dual.py
index 0e58d39af..593b02680 100644
--- a/tests/configs/tsunami-simple-atomic-dual.py
+++ b/tests/configs/tsunami-simple-atomic-dual.py
@@ -62,8 +62,8 @@ class IOCache(BaseCache):
     mshrs = 20
     size = '1kB'
     tgts_per_mshr = 12
-    mem_side_filter_ranges=[AddrRange(0, Addr.max)]
-    cpu_side_filter_ranges=[AddrRange(0x8000000000, Addr.max)]
+    addr_range=AddrRange(0, size='8GB')
+    forward_snoops = False
 
 #cpu
 cpus = [ AtomicSimpleCPU(cpu_id=i) for i in xrange(2) ]
diff --git a/tests/configs/tsunami-simple-atomic.py b/tests/configs/tsunami-simple-atomic.py
index 2374734ec..0c6feaeac 100644
--- a/tests/configs/tsunami-simple-atomic.py
+++ b/tests/configs/tsunami-simple-atomic.py
@@ -62,8 +62,8 @@ class IOCache(BaseCache):
     mshrs = 20
     size = '1kB'
     tgts_per_mshr = 12
-    mem_side_filter_ranges=[AddrRange(0, Addr.max)]
-    cpu_side_filter_ranges=[AddrRange(0x8000000000, Addr.max)]
+    addr_range=AddrRange(0, size='8GB')
+    forward_snoops = False
 
 #cpu
 cpu = AtomicSimpleCPU(cpu_id=0)
diff --git a/tests/configs/tsunami-simple-timing-dual.py b/tests/configs/tsunami-simple-timing-dual.py
index d7c4bb6e8..212449914 100644
--- a/tests/configs/tsunami-simple-timing-dual.py
+++ b/tests/configs/tsunami-simple-timing-dual.py
@@ -62,8 +62,8 @@ class IOCache(BaseCache):
     mshrs = 20
     size = '1kB'
     tgts_per_mshr = 12
-    mem_side_filter_ranges=[AddrRange(0, Addr.max)]
-    cpu_side_filter_ranges=[AddrRange(0x8000000000, Addr.max)]
+    addr_range=AddrRange(0, size='8GB')
+    forward_snoops = False
 
 #cpu
 cpus = [ TimingSimpleCPU(cpu_id=i) for i in xrange(2) ]
diff --git a/tests/configs/tsunami-simple-timing.py b/tests/configs/tsunami-simple-timing.py
index 96cd27111..f0eaa08d7 100644
--- a/tests/configs/tsunami-simple-timing.py
+++ b/tests/configs/tsunami-simple-timing.py
@@ -63,8 +63,8 @@ class IOCache(BaseCache):
     mshrs = 20
     size = '1kB'
     tgts_per_mshr = 12
-    mem_side_filter_ranges=[AddrRange(0, Addr.max)]
-    cpu_side_filter_ranges=[AddrRange(0x8000000000, Addr.max)]
+    addr_range=AddrRange(0, size='8GB')
+    forward_snoops = False
 
 #cpu
 cpu = TimingSimpleCPU(cpu_id=0)