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authorGabe Black <gblack@eecs.umich.edu>2012-01-30 21:07:57 -0800
committerGabe Black <gblack@eecs.umich.edu>2012-01-30 21:07:57 -0800
commite88165a431a90cf7e33e205794caed898ca6fcb1 (patch)
tree741d1c85c83957add6250af0a208d1b976023e29 /tests/configs
parent39f314cc151b0a05ee0e654d52bad1c906fac668 (diff)
parentade53def9252a36a39b2c4bd61196355906f0505 (diff)
downloadgem5-e88165a431a90cf7e33e205794caed898ca6fcb1.tar.xz
Merge with main repository.
Diffstat (limited to 'tests/configs')
-rw-r--r--tests/configs/memtest-ruby.py4
-rw-r--r--tests/configs/o3-timing-mp-ruby.py2
-rw-r--r--tests/configs/o3-timing-ruby.py3
-rw-r--r--tests/configs/rubytest-ruby.py3
-rw-r--r--tests/configs/simple-atomic-mp-ruby.py2
-rw-r--r--tests/configs/simple-timing-mp-ruby.py3
-rw-r--r--tests/configs/simple-timing-ruby.py3
7 files changed, 7 insertions, 13 deletions
diff --git a/tests/configs/memtest-ruby.py b/tests/configs/memtest-ruby.py
index 52eb52904..43031dd02 100644
--- a/tests/configs/memtest-ruby.py
+++ b/tests/configs/memtest-ruby.py
@@ -106,10 +106,6 @@ for (i, ruby_port) in enumerate(system.ruby._cpu_ruby_ports):
#
ruby_port.access_phys_mem = False
-
-# Connect the system port for loading of binaries etc
-system.system_port = system.ruby._sys_port_proxy.port
-
# -----------------------
# run simulation
# -----------------------
diff --git a/tests/configs/o3-timing-mp-ruby.py b/tests/configs/o3-timing-mp-ruby.py
index 2f8829db0..cff511bf8 100644
--- a/tests/configs/o3-timing-mp-ruby.py
+++ b/tests/configs/o3-timing-mp-ruby.py
@@ -46,6 +46,8 @@ for cpu in cpus:
# connect memory to membus
system.physmem.port = system.membus.port
+# Connect the system port for loading of binaries etc
+system.system_port = system.membus.port
# -----------------------
# run simulation
diff --git a/tests/configs/o3-timing-ruby.py b/tests/configs/o3-timing-ruby.py
index b967a5080..14b0ff1ab 100644
--- a/tests/configs/o3-timing-ruby.py
+++ b/tests/configs/o3-timing-ruby.py
@@ -43,4 +43,7 @@ system = System(cpu = cpu,
system.physmem.port = system.membus.port
cpu.connectAllPorts(system.membus)
+# Connect the system port for loading of binaries etc
+system.system_port = system.membus.port
+
root = Root(full_system = False, system = system)
diff --git a/tests/configs/rubytest-ruby.py b/tests/configs/rubytest-ruby.py
index 2531a30c8..116afa2b6 100644
--- a/tests/configs/rubytest-ruby.py
+++ b/tests/configs/rubytest-ruby.py
@@ -102,9 +102,6 @@ for ruby_port in system.ruby._cpu_ruby_ports:
#
ruby_port.access_phys_mem = False
-# Connect the system port for loading of binaries etc
-system.system_port = system.ruby._sys_port_proxy.port
-
# -----------------------
# run simulation
# -----------------------
diff --git a/tests/configs/simple-atomic-mp-ruby.py b/tests/configs/simple-atomic-mp-ruby.py
index fe0311801..8b61fd1f2 100644
--- a/tests/configs/simple-atomic-mp-ruby.py
+++ b/tests/configs/simple-atomic-mp-ruby.py
@@ -47,6 +47,8 @@ for cpu in cpus:
# connect memory to membus
system.physmem.port = system.membus.port
+# Connect the system port for loading of binaries etc
+system.system_port = system.membus.port
# -----------------------
# run simulation
diff --git a/tests/configs/simple-timing-mp-ruby.py b/tests/configs/simple-timing-mp-ruby.py
index c57ffd1f2..9919cabcb 100644
--- a/tests/configs/simple-timing-mp-ruby.py
+++ b/tests/configs/simple-timing-mp-ruby.py
@@ -85,9 +85,6 @@ for (i, cpu) in enumerate(system.cpu):
cpu.icache_port = system.ruby._cpu_ruby_ports[i].port
cpu.dcache_port = system.ruby._cpu_ruby_ports[i].port
-# Connect the system port for loading of binaries etc
-system.system_port = system.ruby._sys_port_proxy.port
-
# -----------------------
# run simulation
# -----------------------
diff --git a/tests/configs/simple-timing-ruby.py b/tests/configs/simple-timing-ruby.py
index 46436d18c..4f812f209 100644
--- a/tests/configs/simple-timing-ruby.py
+++ b/tests/configs/simple-timing-ruby.py
@@ -81,9 +81,6 @@ assert(len(system.ruby._cpu_ruby_ports) == 1)
#
cpu.connectAllPorts(system.ruby._cpu_ruby_ports[0])
-# Connect the system port for loading of binaries etc
-system.system_port = system.ruby._sys_port_proxy.port
-
# -----------------------
# run simulation
# -----------------------