diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2013-01-31 07:49:14 -0500 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2013-01-31 07:49:14 -0500 |
| commit | c4898b15bcf5458e35f17cb0c3b4185cec0081aa (patch) | |
| tree | 7c95a64cb04c3824fa4e2ac514f52fb92be1f58d /tests/configs | |
| parent | eaa37e611f07a41d97a078bf2588bfe745d83751 (diff) | |
| download | gem5-c4898b15bcf5458e35f17cb0c3b4185cec0081aa.tar.xz | |
mem: Add DDR3 and LPDDR2 DRAM controller configurations
This patch moves the default DRAM parameters from the SimpleDRAM class
to two different subclasses, one for DDR3 and one for LPDDR2. More can
be added as we go forward.
The regressions that previously used the SimpleDRAM are now using
SimpleDDR3 as this is the most similar configuration.
Diffstat (limited to 'tests/configs')
| -rw-r--r-- | tests/configs/inorder-timing.py | 2 | ||||
| -rw-r--r-- | tests/configs/o3-timing-checker.py | 2 | ||||
| -rw-r--r-- | tests/configs/o3-timing-mp.py | 2 | ||||
| -rw-r--r-- | tests/configs/o3-timing.py | 2 | ||||
| -rw-r--r-- | tests/configs/tgen-simple-dram.py | 2 |
5 files changed, 5 insertions, 5 deletions
diff --git a/tests/configs/inorder-timing.py b/tests/configs/inorder-timing.py index a92c61ba1..77c4f3d18 100644 --- a/tests/configs/inorder-timing.py +++ b/tests/configs/inorder-timing.py @@ -39,7 +39,7 @@ cpu.addTwoLevelCacheHierarchy(L1Cache(size = '128kB'), cpu.clock = '2GHz' system = System(cpu = cpu, - physmem = SimpleDRAM(), + physmem = SimpleDDR3(), membus = CoherentBus(), mem_mode = "timing") system.system_port = system.membus.slave diff --git a/tests/configs/o3-timing-checker.py b/tests/configs/o3-timing-checker.py index a33a2ac06..cd15cf66b 100644 --- a/tests/configs/o3-timing-checker.py +++ b/tests/configs/o3-timing-checker.py @@ -52,7 +52,7 @@ cpu.addTwoLevelCacheHierarchy(L1Cache(size = '128kB'), cpu.clock = '2GHz' system = System(cpu = cpu, - physmem = SimpleDRAM(), + physmem = SimpleDDR3(), membus = CoherentBus(), mem_mode = "timing") system.system_port = system.membus.slave diff --git a/tests/configs/o3-timing-mp.py b/tests/configs/o3-timing-mp.py index c3a4929bb..59f91a392 100644 --- a/tests/configs/o3-timing-mp.py +++ b/tests/configs/o3-timing-mp.py @@ -36,7 +36,7 @@ cpus = [ DerivO3CPU(cpu_id=i) for i in xrange(nb_cores) ] # system simulated system = System(cpu = cpus, - physmem = SimpleDRAM(), + physmem = SimpleDDR3(), membus = CoherentBus(), mem_mode = "timing") diff --git a/tests/configs/o3-timing.py b/tests/configs/o3-timing.py index 474d13902..8c3c9abe7 100644 --- a/tests/configs/o3-timing.py +++ b/tests/configs/o3-timing.py @@ -41,7 +41,7 @@ cpu.addTwoLevelCacheHierarchy(L1Cache(size = '128kB'), cpu.clock = '2GHz' system = System(cpu = cpu, - physmem = SimpleDRAM(), + physmem = SimpleDDR3(), membus = CoherentBus(), mem_mode = "timing") system.system_port = system.membus.slave diff --git a/tests/configs/tgen-simple-dram.py b/tests/configs/tgen-simple-dram.py index 0e9edc171..19eb15933 100644 --- a/tests/configs/tgen-simple-dram.py +++ b/tests/configs/tgen-simple-dram.py @@ -48,7 +48,7 @@ require_sim_object("CommMonitor") cpu = TrafficGen(config_file = "tests/quick/se/70.tgen/tgen-simple-dram.cfg") # system simulated -system = System(cpu = cpu, physmem = SimpleDRAM(), +system = System(cpu = cpu, physmem = SimpleDDR3(), membus = NoncoherentBus(clock="1GHz", width = 16)) # add a communication monitor |