Regression: Add an I/O Cache to the full system regressions that have a cache.

--HG--
extra : convert_revision : 8ba96e21be2f602eed8258d410038dbe998ef176

4 files changed, 73 insertions, 0 deletions

diff --git a/tests/configs/tsunami-simple-atomic-dual.py b/tests/configs/tsunami-simple-atomic-dual.py
index de8fe2474..0e58d39af 100644
--- a/tests/configs/tsunami-simple-atomic-dual.py
+++ b/tests/configs/tsunami-simple-atomic-dual.py
@@ -52,10 +52,28 @@ class L2(BaseCache):
     tgts_per_mshr = 16
     write_buffers = 8
 
+# ---------------------
+# I/O Cache
+# ---------------------
+class IOCache(BaseCache):
+    assoc = 8
+    block_size = 64
+    latency = '50ns'
+    mshrs = 20
+    size = '1kB'
+    tgts_per_mshr = 12
+    mem_side_filter_ranges=[AddrRange(0, Addr.max)]
+    cpu_side_filter_ranges=[AddrRange(0x8000000000, Addr.max)]
+
 #cpu
 cpus = [ AtomicSimpleCPU(cpu_id=i) for i in xrange(2) ]
 #the system
 system = FSConfig.makeLinuxAlphaSystem('atomic')
+system.bridge.filter_ranges_a=[AddrRange(0, Addr.max)]
+system.bridge.filter_ranges_b=[AddrRange(0, size='8GB')]
+system.iocache = IOCache()
+system.iocache.cpu_side = system.iobus.port
+system.iocache.mem_side = system.membus.port
 
 system.cpu = cpus
 #create the l1/l2 bus
diff --git a/tests/configs/tsunami-simple-atomic.py b/tests/configs/tsunami-simple-atomic.py
index 2ba50273a..2374734ec 100644
--- a/tests/configs/tsunami-simple-atomic.py
+++ b/tests/configs/tsunami-simple-atomic.py
@@ -52,10 +52,28 @@ class L2(BaseCache):
     tgts_per_mshr = 16
     write_buffers = 8
 
+# ---------------------
+# I/O Cache
+# ---------------------
+class IOCache(BaseCache):
+    assoc = 8
+    block_size = 64
+    latency = '50ns'
+    mshrs = 20
+    size = '1kB'
+    tgts_per_mshr = 12
+    mem_side_filter_ranges=[AddrRange(0, Addr.max)]
+    cpu_side_filter_ranges=[AddrRange(0x8000000000, Addr.max)]
+
 #cpu
 cpu = AtomicSimpleCPU(cpu_id=0)
 #the system
 system = FSConfig.makeLinuxAlphaSystem('atomic')
+system.bridge.filter_ranges_a=[AddrRange(0, Addr.max)]
+system.bridge.filter_ranges_b=[AddrRange(0, size='8GB')]
+system.iocache = IOCache()
+system.iocache.cpu_side = system.iobus.port
+system.iocache.mem_side = system.membus.port
 
 system.cpu = cpu
 #create the l1/l2 bus
diff --git a/tests/configs/tsunami-simple-timing-dual.py b/tests/configs/tsunami-simple-timing-dual.py
index 3b1a4f5cf..d7c4bb6e8 100644
--- a/tests/configs/tsunami-simple-timing-dual.py
+++ b/tests/configs/tsunami-simple-timing-dual.py
@@ -52,10 +52,28 @@ class L2(BaseCache):
     tgts_per_mshr = 16
     write_buffers = 8
 
+# ---------------------
+# I/O Cache
+# ---------------------
+class IOCache(BaseCache):
+    assoc = 8
+    block_size = 64
+    latency = '50ns'
+    mshrs = 20
+    size = '1kB'
+    tgts_per_mshr = 12
+    mem_side_filter_ranges=[AddrRange(0, Addr.max)]
+    cpu_side_filter_ranges=[AddrRange(0x8000000000, Addr.max)]
+
 #cpu
 cpus = [ TimingSimpleCPU(cpu_id=i) for i in xrange(2) ]
 #the system
 system = FSConfig.makeLinuxAlphaSystem('timing')
+system.bridge.filter_ranges_a=[AddrRange(0, Addr.max)]
+system.bridge.filter_ranges_b=[AddrRange(0, size='8GB')]
+system.iocache = IOCache()
+system.iocache.cpu_side = system.iobus.port
+system.iocache.mem_side = system.membus.port
 
 system.cpu = cpus
 #create the l1/l2 bus
diff --git a/tests/configs/tsunami-simple-timing.py b/tests/configs/tsunami-simple-timing.py
index 3f18c6848..96cd27111 100644
--- a/tests/configs/tsunami-simple-timing.py
+++ b/tests/configs/tsunami-simple-timing.py
@@ -53,6 +53,19 @@ class L2(BaseCache):
     tgts_per_mshr = 16
     write_buffers = 8
 
+# ---------------------
+# I/O Cache
+# ---------------------
+class IOCache(BaseCache):
+    assoc = 8
+    block_size = 64
+    latency = '50ns'
+    mshrs = 20
+    size = '1kB'
+    tgts_per_mshr = 12
+    mem_side_filter_ranges=[AddrRange(0, Addr.max)]
+    cpu_side_filter_ranges=[AddrRange(0x8000000000, Addr.max)]
+
 #cpu
 cpu = TimingSimpleCPU(cpu_id=0)
 #the system
@@ -61,6 +74,12 @@ system = FSConfig.makeLinuxAlphaSystem('timing')
 system.cpu = cpu
 #create the l1/l2 bus
 system.toL2Bus = Bus()
+system.bridge.filter_ranges_a=[AddrRange(0, Addr.max)]
+system.bridge.filter_ranges_b=[AddrRange(0, size='8GB')]
+system.iocache = IOCache()
+system.iocache.cpu_side = system.iobus.port
+system.iocache.mem_side = system.membus.port
+
 
 #connect up the l2 cache
 system.l2c = L2(size='4MB', assoc=8)