PhysicalMemory has vector of uniform ports instead of one special one.

configs/example/memtest.py:
    PhysicalMemory has vector of uniform ports instead of one special one.
    Other updates to fix obsolete brokenness.
src/mem/physical.cc:
src/mem/physical.hh:
src/python/m5/objects/PhysicalMemory.py:
    Have vector of uniform ports instead of one special one.
src/python/swig/pyobject.cc:
    Add comment.

--HG--
extra : convert_revision : a4a764dcdcd9720bcd07c979d0ece311fc8cb4f1

1 files changed, 3 insertions, 8 deletions

diff --git a/tests/configs/memtest.py b/tests/configs/memtest.py
index 15a4f8f05..6fe244acf 100644
--- a/tests/configs/memtest.py
+++ b/tests/configs/memtest.py
@@ -57,7 +57,8 @@ cpus = [ MemTest() for i in xrange(nb_cores) ]
 
 # system simulated
 system = System(cpu = cpus, funcmem = PhysicalMemory(),
-                physmem = PhysicalMemory(), membus = Bus(clock="500GHz", width=16))
+                physmem = PhysicalMemory(),
+                membus = Bus(clock="500GHz", width=16))
 
 # l2cache & bus
 system.toL2Bus = Bus(clock="500GHz", width=16)
@@ -67,18 +68,12 @@ system.l2c.cpu_side = system.toL2Bus.port
 # connect l2c to membus
 system.l2c.mem_side = system.membus.port
 
-which_port = 0
 # add L1 caches
 for cpu in cpus:
     cpu.l1c = L1(size = '32kB', assoc = 4)
     cpu.l1c.cpu_side = cpu.test
     cpu.l1c.mem_side = system.toL2Bus.port
-    if  which_port == 0:
-         system.funcmem.port = cpu.functional
-         which_port = 1
-    else:
-         system.funcmem.functional = cpu.functional
-
+    system.funcmem.port = cpu.functional
 
 # connect memory to membus
 system.physmem.port = system.membus.port