diff options
author | Nikos Nikoleris <nikos.nikoleris@arm.com> | 2017-03-30 14:24:04 +0100 |
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committer | Nikos Nikoleris <nikos.nikoleris@arm.com> | 2017-06-13 15:55:10 +0000 |
commit | 04a58ded65e3a5f692f730eed87ee0476643c9fe (patch) | |
tree | b8f5d9b60d8b76cfa3344998d9e5c942597102e8 /tests/configs | |
parent | c33289c7d50fe6e2c4a0eda7387fe2c8bd4bf393 (diff) | |
download | gem5-04a58ded65e3a5f692f730eed87ee0476643c9fe.tar.xz |
tests: Add ARM MOESI_CMP_directory regressions
Change-Id: I3d9c1249a2d39f20fb60c4d4e8af7d1d5731dbef
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/2908
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Diffstat (limited to 'tests/configs')
-rw-r--r-- | tests/configs/arm_generic.py | 6 | ||||
-rw-r--r-- | tests/configs/base_config.py | 76 | ||||
-rw-r--r-- | tests/configs/realview-simple-timing-dual-ruby.py | 46 | ||||
-rw-r--r-- | tests/configs/realview-simple-timing-ruby.py | 45 | ||||
-rw-r--r-- | tests/configs/realview64-simple-timing-dual-ruby.py | 47 | ||||
-rw-r--r-- | tests/configs/realview64-simple-timing-ruby.py | 46 |
6 files changed, 246 insertions, 20 deletions
diff --git a/tests/configs/arm_generic.py b/tests/configs/arm_generic.py index 12a876a48..86ad5d7a6 100644 --- a/tests/configs/arm_generic.py +++ b/tests/configs/arm_generic.py @@ -1,4 +1,4 @@ -# Copyright (c) 2012 ARM Limited +# Copyright (c) 2012, 2017 ARM Limited # All rights reserved. # # The license below extends only to copyright in the software and shall @@ -76,16 +76,18 @@ class LinuxArmSystemBuilder(object): Arguments: machine_type -- String describing the platform to simulate num_cpus -- integer number of CPUs in the system + use_ruby -- True if ruby is used instead of the classic memory system """ self.machine_type = machine_type self.num_cpus = kwargs.get('num_cpus', 1) self.mem_size = kwargs.get('mem_size', '256MB') + self.use_ruby = kwargs.get('use_ruby', False) def create_system(self): sc = SysConfig(None, self.mem_size, None) system = FSConfig.makeArmSystem(self.mem_mode, self.machine_type, self.num_cpus, - sc, False) + sc, False, ruby=self.use_ruby) # We typically want the simulator to panic if the kernel # panics or oopses. This prevents the simulator from running diff --git a/tests/configs/base_config.py b/tests/configs/base_config.py index 6af6408fe..2ec041cfc 100644 --- a/tests/configs/base_config.py +++ b/tests/configs/base_config.py @@ -1,4 +1,4 @@ -# Copyright (c) 2012-2013 ARM Limited +# Copyright (c) 2012-2013, 2017 ARM Limited # All rights reserved. # # The license below extends only to copyright in the software and shall @@ -37,12 +37,15 @@ # Andreas Hansson from abc import ABCMeta, abstractmethod +import optparse import m5 from m5.objects import * from m5.proxy import * m5.util.addToPath('../configs/') from common import FSConfig +from common import Options from common.Caches import * +from ruby import Ruby _have_kvm_support = 'BaseKvmCPU' in globals() @@ -59,8 +62,7 @@ class BaseSystem(object): def __init__(self, mem_mode='timing', mem_class=SimpleMemory, cpu_class=TimingSimpleCPU, num_cpus=1, num_threads=1, - checker=False, - mem_size=None): + checker=False, mem_size=None, use_ruby=False): """Initialize a simple base system. Keyword Arguments: @@ -70,6 +72,7 @@ class BaseSystem(object): num_cpus -- Number of CPUs to instantiate checker -- Set to True to add checker CPUs mem_size -- Override the default memory size + use_ruby -- Set to True to use ruby memory """ self.mem_mode = mem_mode self.mem_class = mem_class @@ -77,6 +80,7 @@ class BaseSystem(object): self.num_cpus = num_cpus self.num_threads = num_threads self.checker = checker + self.use_ruby = use_ruby def create_cpus(self, cpu_clk_domain): """Return a list of CPU objects to add to a system.""" @@ -148,10 +152,40 @@ class BaseSystem(object): any([isinstance(c, BaseKvmCPU) for c in system.cpu]): self.init_kvm(system) - sha_bus = self.create_caches_shared(system) + if self.use_ruby: + # Add the ruby specific and protocol specific options + parser = optparse.OptionParser() + Options.addCommonOptions(parser) + Ruby.define_options(parser) + (options, args) = parser.parse_args() + + # Set the default cache size and associativity to be very + # small to encourage races between requests and writebacks. + options.l1d_size="32kB" + options.l1i_size="32kB" + options.l2_size="4MB" + options.l1d_assoc=4 + options.l1i_assoc=2 + options.l2_assoc=8 + options.num_cpus = self.num_cpus + options.num_dirs = 2 + + Ruby.create_system(options, True, system, system.iobus, + system._dma_ports) + + # Create a seperate clock domain for Ruby + system.ruby.clk_domain = SrcClockDomain( + clock = options.ruby_clock, + voltage_domain = system.voltage_domain) + for i, cpu in enumerate(system.cpu): + if not cpu.switched_out: + cpu.createInterruptController() + cpu.connectCachedPorts(system.ruby._cpu_ports[i]) + else: + sha_bus = self.create_caches_shared(system) + for cpu in system.cpu: + self.init_cpu(system, cpu, sha_bus) - for cpu in system.cpu: - self.init_cpu(system, cpu, sha_bus) def create_clk_src(self,system): # Create system clock domain. This provides clock value to every @@ -193,7 +227,8 @@ class BaseSESystem(BaseSystem): membus = SystemXBar(), mem_mode = self.mem_mode, multi_thread = (self.num_threads > 1)) - system.system_port = system.membus.slave + if not self.use_ruby: + system.system_port = system.membus.slave system.physmem.port = system.membus.master self.init_system(system) return system @@ -233,17 +268,22 @@ class BaseFSSystem(BaseSystem): def init_system(self, system): BaseSystem.init_system(self, system) - # create the memory controllers and connect them, stick with - # the physmem name to avoid bumping all the reference stats - system.physmem = [self.mem_class(range = r) - for r in system.mem_ranges] - for i in xrange(len(system.physmem)): - system.physmem[i].port = system.membus.master - - # create the iocache, which by default runs at the system clock - system.iocache = IOCache(addr_ranges=system.mem_ranges) - system.iocache.cpu_side = system.iobus.master - system.iocache.mem_side = system.membus.slave + if self.use_ruby: + # Connect the ruby io port to the PIO bus, + # assuming that there is just one such port. + system.iobus.master = system.ruby._io_port.slave + else: + # create the memory controllers and connect them, stick with + # the physmem name to avoid bumping all the reference stats + system.physmem = [self.mem_class(range = r) + for r in system.mem_ranges] + for i in xrange(len(system.physmem)): + system.physmem[i].port = system.membus.master + + # create the iocache, which by default runs at the system clock + system.iocache = IOCache(addr_ranges=system.mem_ranges) + system.iocache.cpu_side = system.iobus.master + system.iocache.mem_side = system.membus.slave def create_root(self): system = self.create_system() diff --git a/tests/configs/realview-simple-timing-dual-ruby.py b/tests/configs/realview-simple-timing-dual-ruby.py new file mode 100644 index 000000000..d762fa651 --- /dev/null +++ b/tests/configs/realview-simple-timing-dual-ruby.py @@ -0,0 +1,46 @@ +# Copyright (c) 2017 ARM Limited +# All rights reserved. +# +# The license below extends only to copyright in the software and shall +# not be construed as granting a license to any other intellectual +# property including but not limited to intellectual property relating +# to a hardware implementation of the functionality of the software +# licensed hereunder. You may use the software subject to the license +# terms below provided that you ensure that this notice is replicated +# unmodified and in its entirety in all distributions of the software, +# modified or unmodified, in source code or in binary form. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer; +# redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution; +# neither the name of the copyright holders nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Andreas Sandberg + +from m5.objects import * +from arm_generic import * + +root = LinuxArmFSSystem(mem_mode='timing', + mem_class=DDR3_1600_8x8, + cpu_class=TimingSimpleCPU, + num_cpus=2, + use_ruby=True).create_root() + diff --git a/tests/configs/realview-simple-timing-ruby.py b/tests/configs/realview-simple-timing-ruby.py new file mode 100644 index 000000000..41195ef9a --- /dev/null +++ b/tests/configs/realview-simple-timing-ruby.py @@ -0,0 +1,45 @@ +# Copyright (c) 2017 ARM Limited +# All rights reserved. +# +# The license below extends only to copyright in the software and shall +# not be construed as granting a license to any other intellectual +# property including but not limited to intellectual property relating +# to a hardware implementation of the functionality of the software +# licensed hereunder. You may use the software subject to the license +# terms below provided that you ensure that this notice is replicated +# unmodified and in its entirety in all distributions of the software, +# modified or unmodified, in source code or in binary form. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer; +# redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution; +# neither the name of the copyright holders nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Andreas Sandberg + +from m5.objects import * +from arm_generic import * + +root = LinuxArmFSSystemUniprocessor(mem_mode='timing', + mem_class=DDR3_1600_8x8, + cpu_class=TimingSimpleCPU, + use_ruby=True).create_root() + diff --git a/tests/configs/realview64-simple-timing-dual-ruby.py b/tests/configs/realview64-simple-timing-dual-ruby.py new file mode 100644 index 000000000..234e9767b --- /dev/null +++ b/tests/configs/realview64-simple-timing-dual-ruby.py @@ -0,0 +1,47 @@ +# Copyright (c) 2017 ARM Limited +# All rights reserved. +# +# The license below extends only to copyright in the software and shall +# not be construed as granting a license to any other intellectual +# property including but not limited to intellectual property relating +# to a hardware implementation of the functionality of the software +# licensed hereunder. You may use the software subject to the license +# terms below provided that you ensure that this notice is replicated +# unmodified and in its entirety in all distributions of the software, +# modified or unmodified, in source code or in binary form. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer; +# redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution; +# neither the name of the copyright holders nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Andreas Sandberg + +from m5.objects import * +from arm_generic import * + +root = LinuxArmFSSystem(machine_type='VExpress_EMM64', + mem_mode='timing', + mem_class=DDR3_1600_8x8, + cpu_class=TimingSimpleCPU, + num_cpus=2, + use_ruby=True).create_root() + diff --git a/tests/configs/realview64-simple-timing-ruby.py b/tests/configs/realview64-simple-timing-ruby.py new file mode 100644 index 000000000..f2ec90fba --- /dev/null +++ b/tests/configs/realview64-simple-timing-ruby.py @@ -0,0 +1,46 @@ +# Copyright (c) 2017 ARM Limited +# All rights reserved. +# +# The license below extends only to copyright in the software and shall +# not be construed as granting a license to any other intellectual +# property including but not limited to intellectual property relating +# to a hardware implementation of the functionality of the software +# licensed hereunder. You may use the software subject to the license +# terms below provided that you ensure that this notice is replicated +# unmodified and in its entirety in all distributions of the software, +# modified or unmodified, in source code or in binary form. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer; +# redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution; +# neither the name of the copyright holders nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Andreas Sandberg + +from m5.objects import * +from arm_generic import * + +root = LinuxArmFSSystemUniprocessor(machine_type='VExpress_EMM64', + mem_mode='timing', + mem_class=DDR3_1600_8x8, + cpu_class=TimingSimpleCPU, + use_ruby=True).create_root() + |