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authorRon Dreslinski <rdreslin@umich.edu>2006-08-16 23:46:54 -0400
committerRon Dreslinski <rdreslin@umich.edu>2006-08-16 23:46:54 -0400
commit6eebfda2d9a4613d8357a2f266289311240a0a1b (patch)
tree4bb45817a216962eed9506cd4fdb088b620a2902 /tests/configs
parent3329f6f63910963bafd52244df16348667d2e6eb (diff)
downloadgem5-6eebfda2d9a4613d8357a2f266289311240a0a1b.tar.xz
Fix the caches not working in the regression
src/python/m5/objects/BaseCPU.py: Make mem parameter a MemObject, not just a PhysicalMemory Fix a reference not using self tests/configs/simple-atomic.py: Set the mem paramter tests/configs/simple-timing.py: Set the mem parameter --HG-- extra : convert_revision : 6bd9df36831a1c5bafc9e88ab945c2ebe91db785
Diffstat (limited to 'tests/configs')
-rw-r--r--tests/configs/simple-atomic.py1
-rw-r--r--tests/configs/simple-timing.py2
2 files changed, 2 insertions, 1 deletions
diff --git a/tests/configs/simple-atomic.py b/tests/configs/simple-atomic.py
index 9b7ce1429..2bf67f3b1 100644
--- a/tests/configs/simple-atomic.py
+++ b/tests/configs/simple-atomic.py
@@ -34,5 +34,6 @@ system = System(cpu = AtomicSimpleCPU(),
membus = Bus())
system.physmem.port = system.membus.port
system.cpu.connectMemPorts(system.membus)
+system.cpu.mem = system.physmem
root = Root(system = system)
diff --git a/tests/configs/simple-timing.py b/tests/configs/simple-timing.py
index 823a8aec1..78dfabe3b 100644
--- a/tests/configs/simple-timing.py
+++ b/tests/configs/simple-timing.py
@@ -39,7 +39,7 @@ class MyCache(BaseCache):
cpu = TimingSimpleCPU()
cpu.addTwoLevelCacheHierarchy(MyCache(size = '128kB'), MyCache(size = '256kB'),
MyCache(size = '2MB'))
-
+cpu.mem = cpu.dcache
system = System(cpu = cpu,
physmem = PhysicalMemory(),
membus = Bus())