config: Remove redundant explicit setting of default clocks

This patch removes the explicit setting of the clock period for
certain instances of CoherentBus, NonCoherentBus and IOCache where the
specified clock is same as the default value of the system clock. As
all the values used are the defaults, there are no performance
changes. There are similar cases where the toL2Bus is set to use the
parent CPU clock which is already the default behaviour.

The main motivation for these simplifications is to ease the
introduction of clock domains.

4 files changed, 5 insertions, 5 deletions

diff --git a/tests/configs/base_config.py b/tests/configs/base_config.py
index 29aec35e7..60ba31665 100644
--- a/tests/configs/base_config.py
+++ b/tests/configs/base_config.py
@@ -161,8 +161,8 @@ class BaseFSSystem(BaseSystem):
     def init_system(self, system):
         BaseSystem.init_system(self, system)
 
-        #create the iocache
-        system.iocache = IOCache(clock='1GHz', addr_ranges=system.mem_ranges)
+        # create the iocache, which by default runs at the system clock
+        system.iocache = IOCache(addr_ranges=system.mem_ranges)
         system.iocache.cpu_side = system.iobus.master
         system.iocache.mem_side = system.membus.slave
 
diff --git a/tests/configs/memtest.py b/tests/configs/memtest.py
index 55c086d69..379b1e421 100644
--- a/tests/configs/memtest.py
+++ b/tests/configs/memtest.py
@@ -39,7 +39,7 @@ cpus = [ MemTest(clock = '2GHz') for i in xrange(nb_cores) ]
 system = System(cpu = cpus, funcmem = SimpleMemory(in_addr_map = False),
                 funcbus = NoncoherentBus(),
                 physmem = SimpleMemory(),
-                membus = CoherentBus(clock="1GHz", width=16))
+                membus = CoherentBus(width=16))
 
 # l2cache & bus
 system.toL2Bus = CoherentBus(clock="2GHz", width=16)
diff --git a/tests/configs/tgen-simple-dram.py b/tests/configs/tgen-simple-dram.py
index 407852682..b57817c95 100644
--- a/tests/configs/tgen-simple-dram.py
+++ b/tests/configs/tgen-simple-dram.py
@@ -49,7 +49,7 @@ cpu = TrafficGen(config_file = "tests/quick/se/70.tgen/tgen-simple-dram.cfg")
 
 # system simulated
 system = System(cpu = cpu, physmem = DDR3_1600_x64(),
-                membus = NoncoherentBus(clock="1GHz", width = 16))
+                membus = NoncoherentBus(width = 16))
 
 # add a communication monitor
 system.monitor = CommMonitor()
diff --git a/tests/configs/tgen-simple-mem.py b/tests/configs/tgen-simple-mem.py
index d402e557c..200834ec3 100644
--- a/tests/configs/tgen-simple-mem.py
+++ b/tests/configs/tgen-simple-mem.py
@@ -49,7 +49,7 @@ cpu = TrafficGen(config_file = "tests/quick/se/70.tgen/tgen-simple-mem.cfg")
 
 # system simulated
 system = System(cpu = cpu, physmem = SimpleMemory(),
-                membus = NoncoherentBus(clock="1GHz", width = 16))
+                membus = NoncoherentBus(width = 16))
 
 # add a communication monitor, and also trace all the packets
 system.monitor = CommMonitor(trace_file = "monitor.ptrc.gz")