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authorNilay Vaish <nilay@cs.wisc.edu>2013-04-23 00:03:09 -0500
committerNilay Vaish <nilay@cs.wisc.edu>2013-04-23 00:03:09 -0500
commitc2d799c6b06384b2406c0a78da9527649f664519 (patch)
treee4919a1ff6f7da2129052b84cba845d6741773e3 /tests/configs
parent95eebf9e5ef61a8937a3fcca802d25a1c620340b (diff)
downloadgem5-c2d799c6b06384b2406c0a78da9527649f664519.tar.xz
x86: regressions: add switcher full test
Diffstat (limited to 'tests/configs')
-rw-r--r--tests/configs/base_config.py16
-rw-r--r--tests/configs/pc-switcheroo-full.py50
-rw-r--r--tests/configs/x86_generic.py8
3 files changed, 65 insertions, 9 deletions
diff --git a/tests/configs/base_config.py b/tests/configs/base_config.py
index b4c400a45..29aec35e7 100644
--- a/tests/configs/base_config.py
+++ b/tests/configs/base_config.py
@@ -104,14 +104,18 @@ class BaseSystem(object):
system.l2c.mem_side = system.membus.slave
return system.toL2Bus
- def init_cpu(self, system, cpu):
+ def init_cpu(self, system, cpu, sha_bus):
"""Initialize a CPU.
Arguments:
system -- System to work on.
cpu -- CPU to initialize.
"""
- cpu.createInterruptController()
+ if not cpu.switched_out:
+ self.create_caches_private(cpu)
+ cpu.createInterruptController()
+ cpu.connectAllPorts(sha_bus if sha_bus != None else system.membus,
+ system.membus)
def init_kvm(self, system):
"""Do KVM-specific system initialization.
@@ -135,13 +139,7 @@ class BaseSystem(object):
sha_bus = self.create_caches_shared(system)
for cpu in system.cpu:
- if not cpu.switched_out:
- self.create_caches_private(cpu)
- self.init_cpu(system, cpu)
- cpu.connectAllPorts(sha_bus if sha_bus != None else system.membus,
- system.membus)
- else:
- self.init_cpu(system, cpu)
+ self.init_cpu(system, cpu, sha_bus)
@abstractmethod
def create_system(self):
diff --git a/tests/configs/pc-switcheroo-full.py b/tests/configs/pc-switcheroo-full.py
new file mode 100644
index 000000000..c94987638
--- /dev/null
+++ b/tests/configs/pc-switcheroo-full.py
@@ -0,0 +1,50 @@
+# Copyright (c) 2012 ARM Limited
+# Copyright (c) 2013 Mark D. Hill and David A. Wood
+# All rights reserved.
+#
+# The license below extends only to copyright in the software and shall
+# not be construed as granting a license to any other intellectual
+# property including but not limited to intellectual property relating
+# to a hardware implementation of the functionality of the software
+# licensed hereunder. You may use the software subject to the license
+# terms below provided that you ensure that this notice is replicated
+# unmodified and in its entirety in all distributions of the software,
+# modified or unmodified, in source code or in binary form.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Andreas Sandberg
+# Nilay Vaish
+
+from m5.objects import *
+from x86_generic import *
+import switcheroo
+
+root = LinuxX86FSSwitcheroo(
+ cpu_classes=(AtomicSimpleCPU, TimingSimpleCPU, DerivO3CPU)
+ ).create_root()
+
+# Setup a custom test method that uses the switcheroo tester that
+# switches between CPU models.
+run_test = switcheroo.run_test
diff --git a/tests/configs/x86_generic.py b/tests/configs/x86_generic.py
index e9e7bff63..9a499cc60 100644
--- a/tests/configs/x86_generic.py
+++ b/tests/configs/x86_generic.py
@@ -107,3 +107,11 @@ class LinuxX86FSSystemUniprocessor(LinuxX86SystemBuilder,
L2Cache(size='4MB', assoc=8),
PageTableWalkerCache(),
PageTableWalkerCache())
+
+
+class LinuxX86FSSwitcheroo(LinuxX86SystemBuilder, BaseFSSwitcheroo):
+ """Uniprocessor X86 system prepared for CPU switching"""
+
+ def __init__(self, **kwargs):
+ BaseFSSwitcheroo.__init__(self, **kwargs)
+ LinuxX86SystemBuilder.__init__(self)