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authorAndreas Hansson <andreas.hansson@arm.com>2012-09-21 11:48:08 -0400
committerAndreas Hansson <andreas.hansson@arm.com>2012-09-21 11:48:08 -0400
commitd75b1b5a7366c162ffca69b29901f4cb5e05895d (patch)
treefae9c10ca5b245930bfc91098c7edd0cfc386417 /tests/configs
parent4aee3aa073f9a20fff88daf0dd224e5c11d84b4e (diff)
downloadgem5-d75b1b5a7366c162ffca69b29901f4cb5e05895d.tar.xz
TrafficGen: Add a basic traffic generator
This patch adds a traffic generator to the code base. The generator is aimed to be used as a black box model to create appropriate use-cases and benchmarks for the memory system, and in particular the interconnect and the memory controller. The traffic generator is a master module, where the actual behaviour is captured in a state-transition graph where each state generates some sort of traffic. By constructing a graph it is possible to create very elaborate scenarios from basic generators. Currencly the set of generators include idling, linear address sweeps, random address sequences and playback of traces (recording will be done by the Communication Monitor in a follow-up patch). At the moment the graph and the states are described in an ad-hoc line-based format, and in the future this should be aligned with our used of e.g. the Google protobufs. Similarly for the traces, the format is currently a simplistic ad-hoc line-based format that merely serves as a starting point. In addition to being used as a black-box model for system components, the traffic generator is also useful for creating test cases and regressions for the interconnect and memory system. In future patches we will use the traffic generator to create DRAM test cases for the controller model. The patch following this one adds a basic regressions which also contains an example configuration script and trace file for playback.
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