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authorAndreas Hansson <andreas.hansson@arm.com>2013-05-30 12:54:12 -0400
committerAndreas Hansson <andreas.hansson@arm.com>2013-05-30 12:54:12 -0400
commitd82bffd2979ea9dec286dca1b2d10cadc111293a (patch)
treeb52e51f1bbd44202e6a4bd120f2bb7da3741acc6 /tests/configs
parent7da851d1a834fbe6dd02f87884586129786b14a6 (diff)
downloadgem5-d82bffd2979ea9dec286dca1b2d10cadc111293a.tar.xz
mem: Add static latency to the DRAM controller
This patch adds a frontend and backend static latency to the DRAM controller by delaying the responses. Two parameters expressing the frontend and backend contributions in absolute time are added to the controller, and the appropriate latency is added to the responses when adding them to the (infinite) queued port for sending. For writes and reads that hit in the write buffer, only the frontend latency is added. For reads that are serviced by the DRAM, the static latency is the sum of the pipeline latencies of the entire frontend, backend and PHY. The default values are chosen based on having roughly 10 pipeline stages in total at 500 MHz. In the future, it would be sensible to make the controller use its clock and convert these latencies (and a few of the DRAM timings) to cycles.
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