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authorRon Dreslinski <rdreslin@umich.edu>2006-10-09 17:31:58 -0400
committerRon Dreslinski <rdreslin@umich.edu>2006-10-09 17:31:58 -0400
commit727dea78c4b603a63d6c8bee10d317cb2905ffd4 (patch)
tree8b916ef806ce372be7a8875d3e7e6894589bd884 /tests/configs
parentc4dba7a8ed496c2e534b6caa8754678d642124c7 (diff)
downloadgem5-727dea78c4b603a63d6c8bee10d317cb2905ffd4.tar.xz
Update configs for cpu_id
tests/configs/o3-timing-mp.py: tests/configs/simple-atomic-mp.py: tests/configs/simple-timing-mp.py: Update config for cpu_id --HG-- extra : convert_revision : 32a1971997920473164ba12f2b121cb640bad7ac
Diffstat (limited to 'tests/configs')
-rw-r--r--tests/configs/o3-timing-mp.py4
-rw-r--r--tests/configs/simple-atomic-mp.py4
-rw-r--r--tests/configs/simple-timing-mp.py2
3 files changed, 5 insertions, 5 deletions
diff --git a/tests/configs/o3-timing-mp.py b/tests/configs/o3-timing-mp.py
index 881c23156..55af8be0d 100644
--- a/tests/configs/o3-timing-mp.py
+++ b/tests/configs/o3-timing-mp.py
@@ -54,7 +54,7 @@ class L2(BaseCache):
write_buffers = 8
nb_cores = 4
-cpus = [ DetailedO3CPU() for i in xrange(nb_cores) ]
+cpus = [ DetailedO3CPU(cpu_id=i) for i in xrange(nb_cores) ]
# system simulated
system = System(cpu = cpus, physmem = PhysicalMemory(), membus =
@@ -86,5 +86,5 @@ system.physmem.port = system.membus.port
root = Root( system = system )
root.system.mem_mode = 'timing'
-root.trace.flags="Bus Cache"
+#root.trace.flags="Bus Cache"
#root.trace.flags = "BusAddrRanges"
diff --git a/tests/configs/simple-atomic-mp.py b/tests/configs/simple-atomic-mp.py
index cc1a36dda..eaa6ec66e 100644
--- a/tests/configs/simple-atomic-mp.py
+++ b/tests/configs/simple-atomic-mp.py
@@ -52,10 +52,10 @@ class L2(BaseCache):
write_buffers = 8
nb_cores = 4
-cpus = [ AtomicSimpleCPU() for i in xrange(nb_cores) ]
+cpus = [ AtomicSimpleCPU(cpu_id=i) for i in xrange(nb_cores) ]
# system simulated
-system = System(cpu = cpus, physmem = PhysicalMemory(), membus =
+system = System(cpu = cpus, physmem = PhysicalMemory(range = AddrRange('1024MB')), membus =
Bus())
# l2cache & bus
diff --git a/tests/configs/simple-timing-mp.py b/tests/configs/simple-timing-mp.py
index 9fc5f3874..8f9ab0dde 100644
--- a/tests/configs/simple-timing-mp.py
+++ b/tests/configs/simple-timing-mp.py
@@ -52,7 +52,7 @@ class L2(BaseCache):
write_buffers = 8
nb_cores = 4
-cpus = [ TimingSimpleCPU() for i in xrange(nb_cores) ]
+cpus = [ TimingSimpleCPU(cpu_id=i) for i in xrange(nb_cores) ]
# system simulated
system = System(cpu = cpus, physmem = PhysicalMemory(), membus =