m5: Regression Tester Update

This patch includes the necessary regression updates to test the new ruby
configuration system.  The patch includes support for multiple ruby protocols
and adds the ruby random tester.  The patch removes atomic mode test for
ruby since ruby does not support atomic mode acceses.  These tests can be
added back in when ruby supports atomic mode for real.

--HG--
rename : tests/quick/50.memtest/test.py => tests/quick/60.rubytest/test.py

6 files changed, 213 insertions, 89 deletions

diff --git a/tests/configs/memtest-ruby.py b/tests/configs/memtest-ruby.py
index dd402498e..c34eefe5e 100644
--- a/tests/configs/memtest-ruby.py
+++ b/tests/configs/memtest-ruby.py
@@ -1,4 +1,5 @@
 # Copyright (c) 2006-2007 The Regents of The University of Michigan
+# Copyright (c) 2010 Advanced Micro Devices, Inc.
 # All rights reserved.
 #
 # Redistribution and use in source and binary forms, with or without
@@ -63,7 +64,11 @@ execfile(os.path.join(config_root, "configs/common", "Options.py"))
 
 #MAX CORES IS 8 with the fals sharing method
 nb_cores = 8
-cpus = [ MemTest() for i in xrange(nb_cores) ]
+
+# ruby does not support atomic, functional, or uncacheable accesses
+cpus = [ MemTest(atomic=False, percent_functional=0, \
+                 percent_uncacheable=0) \
+         for i in xrange(nb_cores) ]
 
 # overwrite options.num_cpus with the nb_cores value
 options.num_cpus = nb_cores
@@ -91,3 +96,6 @@ for (i, ruby_port) in enumerate(system.ruby.cpu_ruby_ports):
 
 root = Root(system = system)
 root.system.mem_mode = 'timing'
+
+# Not much point in this being higher than the L1 latency
+m5.ticks.setGlobalFrequency('1ns')
diff --git a/tests/configs/ruby_config.py b/tests/configs/ruby_config.py
deleted file mode 100644
index 190337e67..000000000
--- a/tests/configs/ruby_config.py
+++ /dev/null
@@ -1,30 +0,0 @@
-import os
-import subprocess
-
-from os.path import dirname, join as joinpath
-
-import m5
-from m5.params import *
-
-def generate(config_file, cores=1, memories=1, memory_size=1024, \
-             cache_size=32768, cache_assoc=8, dmas=1,
-             ruby_tick='1t', ports_per_cpu=2, protocol='MOESI_CMP_directory'):
-    default = joinpath(dirname(__file__), '../../src/mem/ruby/config')
-    ruby_config = os.environ.get('RUBY_CONFIG', default)
-    args = [ "ruby", "-I", ruby_config, joinpath(ruby_config, "print_cfg.rb"),
-             "-c", str(protocol),
-             "-r", joinpath(ruby_config, config_file), "-p", str(cores),
-             "-m", str(memories), "-s", str(memory_size), "-C", str(cache_size),
-             "-A", str(cache_assoc), "-D", str(dmas)]
-
-    temp_config = joinpath(m5.options.outdir, "ruby.config")
-    ret = subprocess.call(args, stdout=file(temp_config, "w"))
-    if ret != 0:
-        raise RuntimeError, "subprocess failed!"
-
-    return m5.objects.RubyMemory(clock = ruby_tick,
-                                 config_file = temp_config,
-                                 num_cpus = cores,
-                                 range = AddrRange(str(memory_size)+"MB"),
-                                 num_dmas = dmas,
-                                 ports_per_core = ports_per_cpu)
diff --git a/tests/configs/rubytest-ruby.py b/tests/configs/rubytest-ruby.py
new file mode 100644
index 000000000..cd485f819
--- /dev/null
+++ b/tests/configs/rubytest-ruby.py
@@ -0,0 +1,103 @@
+# Copyright (c) 2006-2007 The Regents of The University of Michigan
+# Copyright (c) 2009 Advanced Micro Devices, Inc.
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Ron Dreslinski
+#          Brad Beckmann
+
+import m5
+from m5.objects import *
+from m5.defines import buildEnv
+from m5.util import addToPath
+import os, optparse, sys
+
+if buildEnv['FULL_SYSTEM']:
+    panic("This script requires system-emulation mode (*_SE).")
+
+# Get paths we might need.  It's expected this file is in m5/configs/example.
+config_path = os.path.dirname(os.path.abspath(__file__))
+config_root = os.path.dirname(config_path)
+m5_root = os.path.dirname(config_root)
+addToPath(config_root+'/configs/common')
+addToPath(config_root+'/configs/ruby')
+
+import Ruby
+
+parser = optparse.OptionParser()
+
+#
+# Set the default cache size and associativity to be very small to encourage
+# races between requests and writebacks.
+#
+parser.add_option("--l1d_size", type="string", default="256B")
+parser.add_option("--l1i_size", type="string", default="256B")
+parser.add_option("--l2_size", type="string", default="512B")
+parser.add_option("--l1d_assoc", type="int", default=2)
+parser.add_option("--l1i_assoc", type="int", default=2)
+parser.add_option("--l2_assoc", type="int", default=2)
+
+execfile(os.path.join(config_root, "configs/common", "Options.py"))
+
+(options, args) = parser.parse_args()
+
+#
+# create the tester and system, including ruby
+#
+tester = RubyTester(checks_to_complete = 100, wakeup_frequency = 10)
+
+system = System(physmem = PhysicalMemory())
+
+system.ruby = Ruby.create_system(options, system.physmem)
+
+assert(options.num_cpus == len(system.ruby.cpu_ruby_ports))
+
+#
+# The tester is most effective when randomization is turned on and
+# artifical delay is randomly inserted on messages
+#
+system.ruby.randomization = True
+
+for ruby_port in system.ruby.cpu_ruby_ports:
+    #
+    # Tie the ruby tester ports to the ruby cpu ports
+    #
+    tester.cpuPort = ruby_port.port
+
+    #
+    # Tell the sequencer this is the ruby tester so that it
+    # copies the subblock back to the checker
+    #
+    ruby_port.using_ruby_tester = True
+
+# -----------------------
+# run simulation
+# -----------------------
+
+root = Root( system = system )
+root.system.mem_mode = 'timing'
+
+# Not much point in this being higher than the L1 latency
+m5.ticks.setGlobalFrequency('1ns')
diff --git a/tests/configs/simple-atomic-ruby.py b/tests/configs/simple-atomic-ruby.py
deleted file mode 100644
index 21d90e56f..000000000
--- a/tests/configs/simple-atomic-ruby.py
+++ /dev/null
@@ -1,42 +0,0 @@
-# Copyright (c) 2006-2007 The Regents of The University of Michigan
-# All rights reserved.
-#
-# Redistribution and use in source and binary forms, with or without
-# modification, are permitted provided that the following conditions are
-# met: redistributions of source code must retain the above copyright
-# notice, this list of conditions and the following disclaimer;
-# redistributions in binary form must reproduce the above copyright
-# notice, this list of conditions and the following disclaimer in the
-# documentation and/or other materials provided with the distribution;
-# neither the name of the copyright holders nor the names of its
-# contributors may be used to endorse or promote products derived from
-# this software without specific prior written permission.
-#
-# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
-# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-#
-# Authors: Steve Reinhardt
-
-import m5
-from m5.objects import *
-
-import ruby_config
-ruby_memory = ruby_config.generate("TwoLevel_SplitL1UnifiedL2.rb", 1)
-
-system = System(cpu = AtomicSimpleCPU(cpu_id=0),
-                physmem = ruby_memory,
-                membus = Bus())
-system.physmem.port = system.membus.port
-system.cpu.connectMemPorts(system.membus)
-system.cpu.clock = '2GHz'
-
-root = Root(system = system)
diff --git a/tests/configs/simple-timing-mp-ruby.py b/tests/configs/simple-timing-mp-ruby.py
index 416983014..caaf13985 100644
--- a/tests/configs/simple-timing-mp-ruby.py
+++ b/tests/configs/simple-timing-mp-ruby.py
@@ -28,24 +28,59 @@
 
 import m5
 from m5.objects import *
+from m5.defines import buildEnv
+from m5.util import addToPath
+import os, optparse, sys
+
+if buildEnv['FULL_SYSTEM']:
+    panic("This script requires system-emulation mode (*_SE).")
+
+# Get paths we might need
+config_path = os.path.dirname(os.path.abspath(__file__))
+config_root = os.path.dirname(config_path)
+m5_root = os.path.dirname(config_root)
+addToPath(config_root+'/configs/common')
+addToPath(config_root+'/configs/ruby')
+
+import Ruby
+
+parser = optparse.OptionParser()
+
+#
+# Set the default cache size and associativity to be very small to encourage
+# races between requests and writebacks.
+#
+parser.add_option("--l1d_size", type="string", default="256B")
+parser.add_option("--l1i_size", type="string", default="256B")
+parser.add_option("--l2_size", type="string", default="512B")
+parser.add_option("--l1d_assoc", type="int", default=2)
+parser.add_option("--l1i_assoc", type="int", default=2)
+parser.add_option("--l2_assoc", type="int", default=2)
+
+execfile(os.path.join(config_root, "configs/common", "Options.py"))
+
+(options, args) = parser.parse_args()
 
 nb_cores = 4
 cpus = [ TimingSimpleCPU(cpu_id=i) for i in xrange(nb_cores) ]
 
-import ruby_config
-ruby_memory = ruby_config.generate("TwoLevel_SplitL1UnifiedL2.rb", nb_cores)
+# overwrite the num_cpus to equal nb_cores
+options.num_cpus = nb_cores
 
 # system simulated
-system = System(cpu = cpus, physmem = ruby_memory, membus = Bus())
+system = System(cpu = cpus,
+                physmem = PhysicalMemory())
 
-# add L1 caches
-for cpu in cpus:
-    cpu.connectMemPorts(system.membus)
-    cpu.clock = '2GHz'
+system.ruby = Ruby.create_system(options, system.physmem)
 
-# connect memory to membus
-system.physmem.port = system.membus.port
+assert(options.num_cpus == len(system.ruby.cpu_ruby_ports))
 
+for (i, cpu) in enumerate(system.cpu):
+    #
+    # Tie the cpu ports to the ruby cpu ports
+    #
+    cpu.icache_port = system.ruby.cpu_ruby_ports[i].port
+    cpu.dcache_port = system.ruby.cpu_ruby_ports[i].port
 
 # -----------------------
 # run simulation
@@ -53,3 +88,6 @@ system.physmem.port = system.membus.port
 
 root = Root( system = system )
 root.system.mem_mode = 'timing'
+
+# Not much point in this being higher than the L1 latency
+m5.ticks.setGlobalFrequency('1ns')
diff --git a/tests/configs/simple-timing-ruby.py b/tests/configs/simple-timing-ruby.py
index de63a8bbb..8ca89cdac 100644
--- a/tests/configs/simple-timing-ruby.py
+++ b/tests/configs/simple-timing-ruby.py
@@ -28,16 +28,63 @@
 
 import m5
 from m5.objects import *
+from m5.defines import buildEnv
+from m5.util import addToPath
+import os, optparse, sys
 
-import ruby_config
-ruby_memory = ruby_config.generate("TwoLevel_SplitL1UnifiedL2.rb", 1)
+if buildEnv['FULL_SYSTEM']:
+    panic("This script requires system-emulation mode (*_SE).")
+
+# Get paths we might need
+config_path = os.path.dirname(os.path.abspath(__file__))
+config_root = os.path.dirname(config_path)
+m5_root = os.path.dirname(config_root)
+addToPath(config_root+'/configs/common')
+addToPath(config_root+'/configs/ruby')
+
+import Ruby
+
+parser = optparse.OptionParser()
+
+#
+# Set the default cache size and associativity to be very small to encourage
+# races between requests and writebacks.
+#
+parser.add_option("--l1d_size", type="string", default="256B")
+parser.add_option("--l1i_size", type="string", default="256B")
+parser.add_option("--l2_size", type="string", default="512B")
+parser.add_option("--l1d_assoc", type="int", default=2)
+parser.add_option("--l1i_assoc", type="int", default=2)
+parser.add_option("--l2_assoc", type="int", default=2)
+
+execfile(os.path.join(config_root, "configs/common", "Options.py"))
+
+(options, args) = parser.parse_args()
+
+# this is a uniprocessor only test
+options.num_cpus = 1
 
 cpu = TimingSimpleCPU(cpu_id=0)
 system = System(cpu = cpu,
-                physmem = ruby_memory,
-                membus = Bus())
-system.physmem.port = system.membus.port
-cpu.connectMemPorts(system.membus)
-cpu.clock = '2GHz'
+                physmem = PhysicalMemory())
+
+system.ruby = Ruby.create_system(options, system.physmem)
+
+assert(len(system.ruby.cpu_ruby_ports) == 1)
+
+#
+# Tie the cpu cache ports to the ruby cpu ports and
+# physmem, respectively
+#
+cpu.icache_port = system.ruby.cpu_ruby_ports[0].port
+cpu.dcache_port = system.ruby.cpu_ruby_ports[0].port
+
+# -----------------------
+# run simulation
+# -----------------------
 
 root = Root(system = system)
+root.system.mem_mode = 'timing'
+
+# Not much point in this being higher than the L1 latency
+m5.ticks.setGlobalFrequency('1ns')