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| author | Ron Dreslinski <rdreslin@umich.edu> | 2006-10-09 17:13:50 -0400 |
|---|---|---|
| committer | Ron Dreslinski <rdreslin@umich.edu> | 2006-10-09 17:13:50 -0400 |
| commit | b9fb4d4870dd45c552fd4cd5e531e9626754f19f (patch) | |
| tree | 3a762d373464c3af4bfdb4787369612f43bfe067 /tests/configs | |
| parent | d7c1557e7e731809ede765ade80d0db748afda4b (diff) | |
| download | gem5-b9fb4d4870dd45c552fd4cd5e531e9626754f19f.tar.xz | |
Make memtest work with 8 memtesters
src/mem/physical.cc:
Update comment to match memtest use
src/python/m5/objects/PhysicalMemory.py:
Make memtester have a way to connect functionally
tests/configs/memtest.py:
Properly create 8 memtesters and connect them to the memory system
--HG--
extra : convert_revision : e5a2dd9c8918d58051b553b5c6a14785d48b34ca
Diffstat (limited to 'tests/configs')
| -rw-r--r-- | tests/configs/memtest.py | 10 |
1 files changed, 8 insertions, 2 deletions
diff --git a/tests/configs/memtest.py b/tests/configs/memtest.py index cfcefbcb9..c5cd0246d 100644 --- a/tests/configs/memtest.py +++ b/tests/configs/memtest.py @@ -51,7 +51,8 @@ class L2(BaseCache): tgts_per_mshr = 16 write_buffers = 8 -nb_cores = 1 +#MAX CORES IS 8 with the fals sharing method +nb_cores = 8 cpus = [ MemTest(max_loads=1e12) for i in xrange(nb_cores) ] # system simulated @@ -66,12 +67,17 @@ system.l2c.cpu_side = system.toL2Bus.port # connect l2c to membus system.l2c.mem_side = system.membus.port +which_port = 0 # add L1 caches for cpu in cpus: cpu.l1c = L1(size = '32kB', assoc = 4) cpu.l1c.cpu_side = cpu.test cpu.l1c.mem_side = system.toL2Bus.port - system.funcmem.port = cpu.functional + if which_port == 0: + system.funcmem.port = cpu.functional + which_port = 1 + else: + system.funcmem.functional = cpu.functional # connect memory to membus |