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| author | Andreas Hansson <andreas.hansson@arm.com> | 2012-10-31 08:39:45 -0400 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2012-10-31 08:39:45 -0400 |
| commit | 4e984e0962f047500a31fc8f2fe7fe83ed232a6b (patch) | |
| tree | 8983ef7cf62b4acef409665dbd7ba31fc7aa8bd2 /tests/configs | |
| parent | ab0bd51315eed6a7853b9dfa44f9fdbe9399ea85 (diff) | |
| download | gem5-4e984e0962f047500a31fc8f2fe7fe83ed232a6b.tar.xz | |
stats: Update stats for fixed simple-atomic-mp config
This patch updates the stats for the regressions that were affected by
the typo in the simple-atomic-mp configuration.
Diffstat (limited to 'tests/configs')
| -rw-r--r-- | tests/configs/simple-atomic-mp.py | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/tests/configs/simple-atomic-mp.py b/tests/configs/simple-atomic-mp.py index 966ae24fe..0324bcc04 100644 --- a/tests/configs/simple-atomic-mp.py +++ b/tests/configs/simple-atomic-mp.py @@ -50,7 +50,7 @@ system.l2c.mem_side = system.membus.slave # add L1 caches for cpu in cpus: cpu.addPrivateSplitL1Caches(L1Cache(size = '32kB', assoc = 1), - L1Caches(size = '32kB', assoc = 4)) + L1Cache(size = '32kB', assoc = 4)) # create the interrupt controller cpu.createInterruptController() # connect cpu level-1 caches to shared level-2 cache |