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| author | Andreas Hansson <andreas.hansson@arm.com> | 2012-09-24 18:03:41 -0400 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2012-09-24 18:03:41 -0400 |
| commit | 103a4a049cb197cf5597d1640aff5aed500f73f0 (patch) | |
| tree | 5718f30c370b07e6253e4a372f4ad83ce512a5a4 /tests/configs | |
| parent | 4095af5fd600dcd497aae67ab5471de75601d052 (diff) | |
| download | gem5-103a4a049cb197cf5597d1640aff5aed500f73f0.tar.xz | |
Regression: Set the clock for twosys-tsunami CPUs
This patch merely adds a clock other than the default 1 Tick for the
CPUs of both the test system and drive system for the twosys-tsunami
regression.
The CPU frequency of the driver system is choosed to be twice that of
the test system to ensure it is not the bottleneck (although in this
case it mostly serves as a demonstration of a two-system setup),
Diffstat (limited to 'tests/configs')
| -rw-r--r-- | tests/configs/twosys-tsunami-simple-atomic.py | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/tests/configs/twosys-tsunami-simple-atomic.py b/tests/configs/twosys-tsunami-simple-atomic.py index d0c90e135..71b139787 100644 --- a/tests/configs/twosys-tsunami-simple-atomic.py +++ b/tests/configs/twosys-tsunami-simple-atomic.py @@ -38,6 +38,7 @@ test_sys.cpu = AtomicSimpleCPU(cpu_id=0) # create the interrupt controller test_sys.cpu.createInterruptController() test_sys.cpu.connectAllPorts(test_sys.membus) +test_sys.cpu.clock = '2GHz' # In contrast to the other (one-system) Tsunami configurations we do # not have an IO cache but instead rely on an IO bridge for accesses # from masters on the IO bus to the memory bus @@ -51,6 +52,7 @@ drive_sys.cpu = AtomicSimpleCPU(cpu_id=0) # create the interrupt controller drive_sys.cpu.createInterruptController() drive_sys.cpu.connectAllPorts(drive_sys.membus) +drive_sys.cpu.clock = '4GHz' drive_sys.iobridge = Bridge(delay='50ns', ranges = [AddrRange(0, '8GB')]) drive_sys.iobridge.slave = drive_sys.iobus.master drive_sys.iobridge.master = drive_sys.membus.slave |