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authorSteve Reinhardt <stever@eecs.umich.edu>2006-08-18 00:16:23 -0400
committerSteve Reinhardt <stever@eecs.umich.edu>2006-08-18 00:16:23 -0400
commit4e3164617ad709cb6d4b0f8fbbdfd596f4d6f236 (patch)
tree9d1e42532d876c646fb91d18b0f70803bb62fd9f /tests/configs
parent2b70b74c9bc575005a26fd727be26e11ac6db032 (diff)
downloadgem5-4e3164617ad709cb6d4b0f8fbbdfd596f4d6f236.tar.xz
Add caches in, fix cpu.mem param
--HG-- extra : convert_revision : 486283d83786807c72bb4601e4b9613b55d8802c
Diffstat (limited to 'tests/configs')
-rw-r--r--tests/configs/simple-atomic.py1
-rw-r--r--tests/configs/simple-timing.py5
-rw-r--r--tests/configs/tsunami-simple-atomic-dual.py1
-rw-r--r--tests/configs/tsunami-simple-atomic.py1
-rw-r--r--tests/configs/tsunami-simple-timing-dual.py1
-rw-r--r--tests/configs/tsunami-simple-timing.py1
6 files changed, 8 insertions, 2 deletions
diff --git a/tests/configs/simple-atomic.py b/tests/configs/simple-atomic.py
index 9b7ce1429..2bf67f3b1 100644
--- a/tests/configs/simple-atomic.py
+++ b/tests/configs/simple-atomic.py
@@ -34,5 +34,6 @@ system = System(cpu = AtomicSimpleCPU(),
membus = Bus())
system.physmem.port = system.membus.port
system.cpu.connectMemPorts(system.membus)
+system.cpu.mem = system.physmem
root = Root(system = system)
diff --git a/tests/configs/simple-timing.py b/tests/configs/simple-timing.py
index 8be0c0b3b..9a5b20e88 100644
--- a/tests/configs/simple-timing.py
+++ b/tests/configs/simple-timing.py
@@ -37,8 +37,9 @@ class MyCache(BaseCache):
tgts_per_mshr = 5
cpu = TimingSimpleCPU()
-#cpu.addTwoLevelCacheHierarchy(MyCache(size = '128kB'), MyCache(size = '256kB'),
-# MyCache(size = '2MB'))
+cpu.addTwoLevelCacheHierarchy(MyCache(size = '128kB'), MyCache(size = '256kB'),
+ MyCache(size = '2MB'))
+cpu.mem = cpu.dcache
system = System(cpu = cpu,
physmem = PhysicalMemory(),
diff --git a/tests/configs/tsunami-simple-atomic-dual.py b/tests/configs/tsunami-simple-atomic-dual.py
index 6bcefd74f..e3945f7dc 100644
--- a/tests/configs/tsunami-simple-atomic-dual.py
+++ b/tests/configs/tsunami-simple-atomic-dual.py
@@ -39,5 +39,6 @@ system = FSConfig.makeLinuxAlphaSystem('atomic')
system.cpu = cpus
for c in cpus:
c.connectMemPorts(system.membus)
+ c.mem = system.physmem
root = Root(clock = '2GHz', system = system)
diff --git a/tests/configs/tsunami-simple-atomic.py b/tests/configs/tsunami-simple-atomic.py
index 67499ac45..ca1dd5c77 100644
--- a/tests/configs/tsunami-simple-atomic.py
+++ b/tests/configs/tsunami-simple-atomic.py
@@ -35,5 +35,6 @@ cpu = AtomicSimpleCPU()
system = FSConfig.makeLinuxAlphaSystem('atomic')
system.cpu = cpu
cpu.connectMemPorts(system.membus)
+cpu.mem = system.physmem
root = Root(clock = '2GHz', system = system)
diff --git a/tests/configs/tsunami-simple-timing-dual.py b/tests/configs/tsunami-simple-timing-dual.py
index 59a783b3a..967d6a2d2 100644
--- a/tests/configs/tsunami-simple-timing-dual.py
+++ b/tests/configs/tsunami-simple-timing-dual.py
@@ -39,5 +39,6 @@ system = FSConfig.makeLinuxAlphaSystem('timing')
system.cpu = cpus
for c in cpus:
c.connectMemPorts(system.membus)
+ c.mem = system.physmem
root = Root(clock = '2GHz', system = system)
diff --git a/tests/configs/tsunami-simple-timing.py b/tests/configs/tsunami-simple-timing.py
index 5dba7508d..b3fc9d105 100644
--- a/tests/configs/tsunami-simple-timing.py
+++ b/tests/configs/tsunami-simple-timing.py
@@ -35,5 +35,6 @@ cpu = TimingSimpleCPU()
system = FSConfig.makeLinuxAlphaSystem('timing')
system.cpu = cpu
cpu.connectMemPorts(system.membus)
+cpu.mem = system.physmem
root = Root(clock = '2GHz', system = system)