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authorAndreas Hansson <andreas.hansson@arm.com>2012-10-15 08:09:57 -0400
committerAndreas Hansson <andreas.hansson@arm.com>2012-10-15 08:09:57 -0400
commit072a91ee51032a2985783d4a17dca6e918ad3023 (patch)
tree79403df95bb85711a1ed193cfdd251bb1bb9934b /tests/configs
parent54227f9e57f625a66e3fd1d0d67fbd53b5408bf2 (diff)
downloadgem5-072a91ee51032a2985783d4a17dca6e918ad3023.tar.xz
Configs: Set the memtest clock to a reasonable value
This patch changes the memtest clock from 1THz (the default) to 2GHz, similar to the CPUs in the other regressions. This is useful as the caches will adopt the same clock as the CPU. The bus clock rate is scaled accordingly, and the L1-L2 bus is kept at the CPU clock while the memory bus is at half that frequency. A separate patch updates the affected stats.
Diffstat (limited to 'tests/configs')
-rw-r--r--tests/configs/memtest-ruby.py2
-rw-r--r--tests/configs/memtest.py6
2 files changed, 4 insertions, 4 deletions
diff --git a/tests/configs/memtest-ruby.py b/tests/configs/memtest-ruby.py
index 560a8fd65..397e9f0c7 100644
--- a/tests/configs/memtest-ruby.py
+++ b/tests/configs/memtest-ruby.py
@@ -69,7 +69,7 @@ options.l3_assoc=2
nb_cores = 8
# ruby does not support atomic, functional, or uncacheable accesses
-cpus = [ MemTest(atomic=False, percent_functional=50,
+cpus = [ MemTest(clock = '2GHz', atomic=False, percent_functional=50,
percent_uncacheable=0, suppress_func_warnings=True) \
for i in xrange(nb_cores) ]
diff --git a/tests/configs/memtest.py b/tests/configs/memtest.py
index f91a7eb78..5d60ee0ea 100644
--- a/tests/configs/memtest.py
+++ b/tests/configs/memtest.py
@@ -55,16 +55,16 @@ class L2(BaseCache):
#MAX CORES IS 8 with the fals sharing method
nb_cores = 8
-cpus = [ MemTest() for i in xrange(nb_cores) ]
+cpus = [ MemTest(clock = '2GHz') for i in xrange(nb_cores) ]
# system simulated
system = System(cpu = cpus, funcmem = SimpleMemory(in_addr_map = False),
funcbus = NoncoherentBus(),
physmem = SimpleMemory(),
- membus = CoherentBus(clock="500GHz", width=16))
+ membus = CoherentBus(clock="1GHz", width=16))
# l2cache & bus
-system.toL2Bus = CoherentBus(clock="500GHz", width=16)
+system.toL2Bus = CoherentBus(clock="2GHz", width=16)
system.l2c = L2(size='64kB', assoc=8)
system.l2c.cpu_side = system.toL2Bus.master