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authorAndreas Sandberg <andreas.sandberg@arm.com>2016-06-02 15:20:24 +0100
committerAndreas Sandberg <andreas.sandberg@arm.com>2016-06-02 15:20:24 +0100
commit1a65e946367d22f3504fcf28d6ba2e7ef597d258 (patch)
tree606e01023627b0b014464c8dc5692605f7ccf573 /tests/configs
parent1d933447fc62de67db938970a8308ac47189fd96 (diff)
downloadgem5-1a65e946367d22f3504fcf28d6ba2e7ef597d258.tar.xz
tests: Remove working dir assumption in tgen tests
The traffic generator tests currently assume that they are run from the root of the source directory. This sometimes breaks tests when they are run using the new test framework. Change-Id: I6538a7902694c5d2c980295e076ea1c09acc4291 Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Curtis Dunham <curtis.dunham@arm.com>
Diffstat (limited to 'tests/configs')
-rw-r--r--tests/configs/tgen-dram-ctrl.py3
-rw-r--r--tests/configs/tgen-simple-mem.py3
2 files changed, 4 insertions, 2 deletions
diff --git a/tests/configs/tgen-dram-ctrl.py b/tests/configs/tgen-dram-ctrl.py
index cd6721e6d..292c7e5b9 100644
--- a/tests/configs/tgen-dram-ctrl.py
+++ b/tests/configs/tgen-dram-ctrl.py
@@ -45,7 +45,8 @@ require_sim_object("CommMonitor")
# even if this is only a traffic generator, call it cpu to make sure
# the scripts are happy
-cpu = TrafficGen(config_file = "tests/quick/se/70.tgen/tgen-dram-ctrl.cfg")
+cpu = TrafficGen(
+ config_file=srcpath("tests/quick/se/70.tgen/tgen-dram-ctrl.cfg"))
# system simulated
system = System(cpu = cpu, physmem = DDR3_1600_x64(),
diff --git a/tests/configs/tgen-simple-mem.py b/tests/configs/tgen-simple-mem.py
index d128eb37d..815bc490c 100644
--- a/tests/configs/tgen-simple-mem.py
+++ b/tests/configs/tgen-simple-mem.py
@@ -45,7 +45,8 @@ require_sim_object("CommMonitor")
# even if this is only a traffic generator, call it cpu to make sure
# the scripts are happy
-cpu = TrafficGen(config_file = "tests/quick/se/70.tgen/tgen-simple-mem.cfg")
+cpu = TrafficGen(
+ config_file=srcpath("tests/quick/se/70.tgen/tgen-simple-mem.cfg"))
# system simulated
system = System(cpu = cpu, physmem = SimpleMemory(),