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| author | Korey Sewell <ksewell@umich.edu> | 2011-02-23 16:35:25 -0500 |
|---|---|---|
| committer | Korey Sewell <ksewell@umich.edu> | 2011-02-23 16:35:25 -0500 |
| commit | 72fb282ab12abf2a1f13c3e9630dff3ffd983863 (patch) | |
| tree | c10af85ebfe17cfe65080f5823fdc155f7f38625 /tests/long/00.gzip/ref/alpha/tru64/inorder-timing/simerr | |
| parent | 0a74246fb9d618ca851122f4f63135fc490f22cd (diff) | |
| download | gem5-72fb282ab12abf2a1f13c3e9630dff3ffd983863.tar.xz | |
inorder: add 00.gzip and 60.bzip2 regression tests
Diffstat (limited to 'tests/long/00.gzip/ref/alpha/tru64/inorder-timing/simerr')
| -rwxr-xr-x | tests/long/00.gzip/ref/alpha/tru64/inorder-timing/simerr | 11 |
1 files changed, 11 insertions, 0 deletions
diff --git a/tests/long/00.gzip/ref/alpha/tru64/inorder-timing/simerr b/tests/long/00.gzip/ref/alpha/tru64/inorder-timing/simerr new file mode 100755 index 000000000..79a2396a6 --- /dev/null +++ b/tests/long/00.gzip/ref/alpha/tru64/inorder-timing/simerr @@ -0,0 +1,11 @@ +warn: Sockets disabled, not accepting gdb connections +For more information see: http://www.m5sim.org/warn/d946bea6 +warn: Prefetch instrutions is Alpha do not do anything +For more information see: http://www.m5sim.org/warn/3e0eccba +warn: Prefetch instrutions is Alpha do not do anything +For more information see: http://www.m5sim.org/warn/3e0eccba +warn: Prefetch instrutions is Alpha do not do anything +For more information see: http://www.m5sim.org/warn/3e0eccba +warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +hack: be nice to actually delete the event here |