diff options
author | Steve Reinhardt <stever@gmail.com> | 2008-02-16 14:58:37 -0500 |
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committer | Steve Reinhardt <stever@gmail.com> | 2008-02-16 14:58:37 -0500 |
commit | 3204f968091d32846a59c0666157c6c8946842d1 (patch) | |
tree | 497c84fa2634b7bcd6c0a5ab03e6d602c264fd07 /tests/long/00.gzip/ref/alpha/tru64/simple-timing | |
parent | 4597a71cef808969c442fca73ae662efe75550d7 (diff) | |
download | gem5-3204f968091d32846a59c0666157c6c8946842d1.tar.xz |
Update stats for new writeback behavior.
--HG--
extra : convert_revision : 3e932b5773f5fb9a119822d5bf497f61e9409c14
Diffstat (limited to 'tests/long/00.gzip/ref/alpha/tru64/simple-timing')
3 files changed, 54 insertions, 55 deletions
diff --git a/tests/long/00.gzip/ref/alpha/tru64/simple-timing/config.ini b/tests/long/00.gzip/ref/alpha/tru64/simple-timing/config.ini index 21fbe2323..b25116443 100644 --- a/tests/long/00.gzip/ref/alpha/tru64/simple-timing/config.ini +++ b/tests/long/00.gzip/ref/alpha/tru64/simple-timing/config.ini @@ -169,6 +169,7 @@ euid=100 executable=/dist/m5/cpu2000/binaries/alpha/tru64/gzip gid=100 input=cin +max_stack_size=67108864 output=cout pid=100 ppid=99 diff --git a/tests/long/00.gzip/ref/alpha/tru64/simple-timing/m5stats.txt b/tests/long/00.gzip/ref/alpha/tru64/simple-timing/m5stats.txt index 9e54c6441..1a22ca151 100644 --- a/tests/long/00.gzip/ref/alpha/tru64/simple-timing/m5stats.txt +++ b/tests/long/00.gzip/ref/alpha/tru64/simple-timing/m5stats.txt @@ -1,21 +1,21 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1400395 # Simulator instruction rate (inst/s) -host_mem_usage 199872 # Number of bytes of host memory used -host_seconds 429.78 # Real time elapsed on the host -host_tick_rate 1787654853 # Simulator tick rate (ticks/s) +host_inst_rate 991240 # Simulator instruction rate (inst/s) +host_mem_usage 177788 # Number of bytes of host memory used +host_seconds 607.18 # Real time elapsed on the host +host_tick_rate 1262504824 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 601856964 # Number of instructions simulated -sim_seconds 0.768293 # Number of seconds simulated -sim_ticks 768292872000 # Number of ticks simulated +sim_seconds 0.766562 # Number of seconds simulated +sim_ticks 766562460000 # Number of ticks simulated system.cpu.dcache.ReadReq_accesses 114514042 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 23626.361612 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 21626.361612 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_miss_latency 15027.272004 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 13027.272004 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_hits 114312810 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 4754380000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency 3023968000 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_rate 0.001757 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_misses 201232 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_miss_latency 4351916000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency 2621504000 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate 0.001757 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_misses 201232 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_accesses 39451321 # number of WriteReq accesses(hits+misses) @@ -37,29 +37,29 @@ system.cpu.dcache.blocked_cycles_no_mshrs 0 # n system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.demand_accesses 153965363 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 24478.573840 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 22478.573840 # average overall mshr miss latency +system.cpu.dcache.demand_avg_miss_latency 21214.403072 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 19214.403072 # average overall mshr miss latency system.cpu.dcache.demand_hits 153435240 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 12976655000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency 11246243000 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_rate 0.003443 # miss rate for demand accesses system.cpu.dcache.demand_misses 530123 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 11916409000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 10185997000 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_rate 0.003443 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_misses 530123 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.overall_accesses 153965363 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 24478.573840 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 22478.573840 # average overall mshr miss latency +system.cpu.dcache.overall_avg_miss_latency 21214.403072 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 19214.403072 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.cpu.dcache.overall_hits 153435240 # number of overall hits -system.cpu.dcache.overall_miss_latency 12976655000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency 11246243000 # number of overall miss cycles system.cpu.dcache.overall_miss_rate 0.003443 # miss rate for overall accesses system.cpu.dcache.overall_misses 530123 # number of overall misses system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 11916409000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 10185997000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_rate 0.003443 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_misses 530123 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -76,9 +76,9 @@ system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.dcache.replacements 451299 # number of replacements system.cpu.dcache.sampled_refs 455395 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 4094.968001 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 4094.968634 # Cycle average of tags in use system.cpu.dcache.total_refs 153509968 # Total number of references to valid blocks. -system.cpu.dcache.warmup_cycle 343385000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.warmup_cycle 342269000 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 325723 # number of writebacks system.cpu.dtb.accesses 153970296 # DTB accesses system.cpu.dtb.acv 0 # DTB access violations @@ -150,7 +150,7 @@ system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.icache.replacements 24 # number of replacements system.cpu.icache.sampled_refs 795 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 673.685273 # Cycle average of tags in use +system.cpu.icache.tagsinuse 673.730766 # Cycle average of tags in use system.cpu.icache.total_refs 601861103 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks @@ -171,30 +171,27 @@ system.cpu.l2cache.ReadExReq_mshr_misses 254163 # nu system.cpu.l2cache.ReadReq_accesses 202027 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_avg_miss_latency 22000 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 11000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_hits 23035 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 3937824000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.885981 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 178992 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 1968912000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.885981 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 178992 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_hits 167236 # number of ReadReq hits +system.cpu.l2cache.ReadReq_miss_latency 765402000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.172210 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 34791 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 382701000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.172210 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 34791 # number of ReadReq MSHR misses system.cpu.l2cache.UpgradeReq_accesses 74728 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_avg_miss_latency 22000 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency 21998.527995 # average UpgradeReq miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 11000 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_miss_latency 1644016000 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency 1643906000 # number of UpgradeReq miss cycles system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_misses 74728 # number of UpgradeReq misses system.cpu.l2cache.UpgradeReq_mshr_miss_latency 822008000 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_mshr_misses 74728 # number of UpgradeReq MSHR misses system.cpu.l2cache.Writeback_accesses 325723 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_miss_rate 1 # miss rate for Writeback accesses -system.cpu.l2cache.Writeback_misses 325723 # number of Writeback misses -system.cpu.l2cache.Writeback_mshr_miss_rate 1 # mshr miss rate for Writeback accesses -system.cpu.l2cache.Writeback_mshr_misses 325723 # number of Writeback MSHR misses +system.cpu.l2cache.Writeback_hits 325723 # number of Writeback hits system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 3.500034 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 3.519863 # Average number of references to valid blocks. system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked @@ -203,14 +200,14 @@ system.cpu.l2cache.cache_copies 0 # nu system.cpu.l2cache.demand_accesses 456190 # number of demand (read+write) accesses system.cpu.l2cache.demand_avg_miss_latency 22000 # average overall miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency 11000 # average overall mshr miss latency -system.cpu.l2cache.demand_hits 23035 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 9529410000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.949506 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 433155 # number of demand (read+write) misses +system.cpu.l2cache.demand_hits 167236 # number of demand (read+write) hits +system.cpu.l2cache.demand_miss_latency 6356988000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.633407 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 288954 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 4764705000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.949506 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 433155 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_miss_latency 3178494000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.633407 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 288954 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate @@ -218,14 +215,14 @@ system.cpu.l2cache.overall_accesses 456190 # nu system.cpu.l2cache.overall_avg_miss_latency 22000 # average overall miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 11000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu.l2cache.overall_hits 23035 # number of overall hits -system.cpu.l2cache.overall_miss_latency 9529410000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.949506 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 433155 # number of overall misses +system.cpu.l2cache.overall_hits 167236 # number of overall hits +system.cpu.l2cache.overall_miss_latency 6356988000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.633407 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 288954 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 4764705000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.949506 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 433155 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_miss_latency 3178494000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.633407 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 288954 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -237,15 +234,15 @@ system.cpu.l2cache.prefetcher.num_hwpf_issued 0 system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.l2cache.replacements 13394 # number of replacements -system.cpu.l2cache.sampled_refs 14881 # Sample count of references to valid blocks. +system.cpu.l2cache.replacements 84513 # number of replacements +system.cpu.l2cache.sampled_refs 100134 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 8423.428104 # Cycle average of tags in use -system.cpu.l2cache.total_refs 52084 # Total number of references to valid blocks. +system.cpu.l2cache.tagsinuse 16358.690190 # Cycle average of tags in use +system.cpu.l2cache.total_refs 352458 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.writebacks 0 # number of writebacks +system.cpu.l2cache.writebacks 63194 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 1536585744 # number of cpu cycles simulated +system.cpu.numCycles 1533124920 # number of cpu cycles simulated system.cpu.num_insts 601856964 # Number of instructions executed system.cpu.num_refs 154866966 # Number of memory references system.cpu.workload.PROG:num_syscalls 17 # Number of system calls diff --git a/tests/long/00.gzip/ref/alpha/tru64/simple-timing/stderr b/tests/long/00.gzip/ref/alpha/tru64/simple-timing/stderr index f33d007a7..5992f7131 100644 --- a/tests/long/00.gzip/ref/alpha/tru64/simple-timing/stderr +++ b/tests/long/00.gzip/ref/alpha/tru64/simple-timing/stderr @@ -1,2 +1,3 @@ +0: system.remote_gdb.listener: listening for remote gdb on port 7000 warn: Entering event queue @ 0. Starting simulation... warn: Increasing stack size by one page. |