diff options
author | Kevin Lim <ktlim@umich.edu> | 2007-04-27 14:35:58 -0400 |
---|---|---|
committer | Kevin Lim <ktlim@umich.edu> | 2007-04-27 14:35:58 -0400 |
commit | 7f39291c81cb65dc166926136c8f3cab253df160 (patch) | |
tree | 8e2ef8eb5b3d3a092025a2a390be07cfc2e3c25b /tests/long/00.gzip/ref/alpha/tru64/simple-timing | |
parent | 522e59840f2d3c44d7d95ebc44b44abebb1212c9 (diff) | |
download | gem5-7f39291c81cb65dc166926136c8f3cab253df160.tar.xz |
Update Alpha reference stats for clock changes.
tests/long/00.gzip/ref/alpha/tru64/o3-timing/config.ini:
tests/long/00.gzip/ref/alpha/tru64/o3-timing/config.out:
tests/long/00.gzip/ref/alpha/tru64/o3-timing/m5stats.txt:
tests/long/00.gzip/ref/alpha/tru64/simple-atomic/config.ini:
tests/long/00.gzip/ref/alpha/tru64/simple-atomic/config.out:
tests/long/00.gzip/ref/alpha/tru64/simple-atomic/m5stats.txt:
tests/long/00.gzip/ref/alpha/tru64/simple-atomic/stderr:
tests/long/00.gzip/ref/alpha/tru64/simple-timing/config.ini:
tests/long/00.gzip/ref/alpha/tru64/simple-timing/config.out:
tests/long/00.gzip/ref/alpha/tru64/simple-timing/m5stats.txt:
tests/long/00.gzip/ref/alpha/tru64/simple-timing/stderr:
tests/long/30.eon/ref/alpha/tru64/o3-timing/config.ini:
tests/long/30.eon/ref/alpha/tru64/o3-timing/config.out:
tests/long/30.eon/ref/alpha/tru64/o3-timing/m5stats.txt:
tests/long/30.eon/ref/alpha/tru64/o3-timing/stdout:
tests/long/30.eon/ref/alpha/tru64/simple-atomic/config.ini:
tests/long/30.eon/ref/alpha/tru64/simple-atomic/config.out:
tests/long/30.eon/ref/alpha/tru64/simple-atomic/m5stats.txt:
tests/long/30.eon/ref/alpha/tru64/simple-atomic/stderr:
tests/long/30.eon/ref/alpha/tru64/simple-atomic/stdout:
tests/long/30.eon/ref/alpha/tru64/simple-timing/config.ini:
tests/long/30.eon/ref/alpha/tru64/simple-timing/config.out:
tests/long/30.eon/ref/alpha/tru64/simple-timing/m5stats.txt:
tests/long/30.eon/ref/alpha/tru64/simple-timing/stderr:
tests/long/30.eon/ref/alpha/tru64/simple-timing/stdout:
tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/config.ini:
tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/config.out:
tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/m5stats.txt:
tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/stderr:
tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/config.ini:
tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/config.out:
tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/m5stats.txt:
tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/stderr:
tests/long/50.vortex/ref/alpha/tru64/o3-timing/config.ini:
tests/long/50.vortex/ref/alpha/tru64/o3-timing/config.out:
tests/long/50.vortex/ref/alpha/tru64/o3-timing/m5stats.txt:
tests/long/50.vortex/ref/alpha/tru64/o3-timing/smred.msg:
tests/long/50.vortex/ref/alpha/tru64/simple-atomic/config.ini:
tests/long/50.vortex/ref/alpha/tru64/simple-atomic/config.out:
tests/long/50.vortex/ref/alpha/tru64/simple-atomic/m5stats.txt:
tests/long/50.vortex/ref/alpha/tru64/simple-atomic/stderr:
tests/long/50.vortex/ref/alpha/tru64/simple-timing/config.ini:
tests/long/50.vortex/ref/alpha/tru64/simple-timing/config.out:
tests/long/50.vortex/ref/alpha/tru64/simple-timing/m5stats.txt:
tests/long/50.vortex/ref/alpha/tru64/simple-timing/stderr:
tests/long/60.bzip2/ref/alpha/tru64/o3-timing/config.ini:
tests/long/60.bzip2/ref/alpha/tru64/o3-timing/config.out:
tests/long/60.bzip2/ref/alpha/tru64/o3-timing/m5stats.txt:
tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/config.ini:
tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/config.out:
tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/m5stats.txt:
tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/stderr:
tests/long/60.bzip2/ref/alpha/tru64/simple-timing/config.ini:
tests/long/60.bzip2/ref/alpha/tru64/simple-timing/config.out:
tests/long/60.bzip2/ref/alpha/tru64/simple-timing/m5stats.txt:
tests/long/60.bzip2/ref/alpha/tru64/simple-timing/stderr:
tests/long/70.twolf/ref/alpha/tru64/o3-timing/config.ini:
tests/long/70.twolf/ref/alpha/tru64/o3-timing/config.out:
tests/long/70.twolf/ref/alpha/tru64/o3-timing/m5stats.txt:
tests/long/70.twolf/ref/alpha/tru64/simple-atomic/config.ini:
tests/long/70.twolf/ref/alpha/tru64/simple-atomic/config.out:
tests/long/70.twolf/ref/alpha/tru64/simple-atomic/m5stats.txt:
tests/long/70.twolf/ref/alpha/tru64/simple-atomic/smred.out:
tests/long/70.twolf/ref/alpha/tru64/simple-atomic/stderr:
tests/long/70.twolf/ref/alpha/tru64/simple-timing/config.ini:
tests/long/70.twolf/ref/alpha/tru64/simple-timing/config.out:
tests/long/70.twolf/ref/alpha/tru64/simple-timing/m5stats.txt:
tests/long/70.twolf/ref/alpha/tru64/simple-timing/smred.out:
tests/long/70.twolf/ref/alpha/tru64/simple-timing/stderr:
Update refs for clock changes.
--HG--
extra : convert_revision : 7c32a3362da60fd12b7bf9219842f707319cda42
Diffstat (limited to 'tests/long/00.gzip/ref/alpha/tru64/simple-timing')
4 files changed, 62 insertions, 160 deletions
diff --git a/tests/long/00.gzip/ref/alpha/tru64/simple-timing/config.ini b/tests/long/00.gzip/ref/alpha/tru64/simple-timing/config.ini index 48a760b08..f70ed5de3 100644 --- a/tests/long/00.gzip/ref/alpha/tru64/simple-timing/config.ini +++ b/tests/long/00.gzip/ref/alpha/tru64/simple-timing/config.ini @@ -1,48 +1,7 @@ [root] type=Root children=system -checkpoint= -clock=1000000000000 -max_tick=0 -output_file=cout -progress_interval=0 - -[exetrace] -intel_format=false -legion_lockstep=false -pc_symbol=true -print_cpseq=false -print_cycle=true -print_data=true -print_effaddr=true -print_fetchseq=false -print_iregs=false -print_opclass=true -print_thread=true -speculative=true -trace_system=client - -[serialize] -count=10 -cycle=0 -dir=cpt.%012d -period=0 - -[stats] -descriptions=true -dump_cycle=0 -dump_period=0 -dump_reset=false -ignore_events= -mysql_db= -mysql_host= -mysql_password= -mysql_user= -project_name=test -simulation_name=test -simulation_sample=0 -text_compat=true -text_file=m5stats.txt +dummy=0 [system] type=System @@ -53,7 +12,7 @@ physmem=system.physmem [system.cpu] type=TimingSimpleCPU children=dcache icache l2cache toL2Bus workload -clock=1 +clock=500 cpu_id=0 defer_registration=false function_trace=false @@ -197,7 +156,7 @@ port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cp [system.cpu.workload] type=LiveProcess cmd=gzip input.log 1 -cwd=build/ALPHA_SE/tests/opt/long/00.gzip/alpha/linux/simple-timing +cwd=build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/simple-timing egid=100 env= euid=100 @@ -223,14 +182,6 @@ type=PhysicalMemory file= latency=1 range=0:134217727 +zero=false port=system.membus.port[0] -[trace] -bufsize=0 -cycle=0 -dump_on_exit=false -file=cout -flags= -ignore= -start=0 - diff --git a/tests/long/00.gzip/ref/alpha/tru64/simple-timing/config.out b/tests/long/00.gzip/ref/alpha/tru64/simple-timing/config.out index eddb9ff53..d4c1bde6e 100644 --- a/tests/long/00.gzip/ref/alpha/tru64/simple-timing/config.out +++ b/tests/long/00.gzip/ref/alpha/tru64/simple-timing/config.out @@ -1,15 +1,13 @@ [root] type=Root -clock=1000000000000 -max_tick=0 -progress_interval=0 -output_file=cout +dummy=0 [system.physmem] type=PhysicalMemory file= range=[0,134217727] latency=1 +zero=false [system] type=System @@ -30,7 +28,7 @@ executable=/dist/m5/cpu2000/binaries/alpha/tru64/gzip input=cin output=cout env= -cwd=build/ALPHA_SE/tests/opt/long/00.gzip/alpha/linux/simple-timing +cwd=build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/simple-timing system=system uid=100 euid=100 @@ -49,7 +47,7 @@ progress_interval=0 system=system cpu_id=0 workload=system.cpu.workload -clock=1 +clock=500 phase=0 defer_registration=false // width not specified @@ -178,51 +176,3 @@ prefetch_use_cpu_id=true prefetch_data_accesses_only=false hit_latency=1 -[trace] -flags= -start=0 -cycle=0 -bufsize=0 -file=cout -dump_on_exit=false -ignore= - -[stats] -descriptions=true -project_name=test -simulation_name=test -simulation_sample=0 -text_file=m5stats.txt -text_compat=true -mysql_db= -mysql_user= -mysql_password= -mysql_host= -events_start=-1 -dump_reset=false -dump_cycle=0 -dump_period=0 -ignore_events= - -[random] -seed=1 - -[exetrace] -speculative=true -print_cycle=true -print_opclass=true -print_thread=true -print_effaddr=true -print_data=true -print_iregs=false -print_fetchseq=false -print_cpseq=false -print_reg_delta=false -pc_symbol=true -intel_format=false -legion_lockstep=false -trace_system=client - -[statsreset] -reset_cycle=0 - diff --git a/tests/long/00.gzip/ref/alpha/tru64/simple-timing/m5stats.txt b/tests/long/00.gzip/ref/alpha/tru64/simple-timing/m5stats.txt index 5e7441c54..5fbf59915 100644 --- a/tests/long/00.gzip/ref/alpha/tru64/simple-timing/m5stats.txt +++ b/tests/long/00.gzip/ref/alpha/tru64/simple-timing/m5stats.txt @@ -1,31 +1,31 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 549029 # Simulator instruction rate (inst/s) -host_mem_usage 300652 # Number of bytes of host memory used -host_seconds 1096.22 # Real time elapsed on the host -host_tick_rate 1916109 # Simulator tick rate (ticks/s) +host_inst_rate 642291 # Simulator instruction rate (inst/s) +host_mem_usage 153996 # Number of bytes of host memory used +host_seconds 937.05 # Real time elapsed on the host +host_tick_rate 404322160 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 601856965 # Number of instructions simulated -sim_seconds 0.002100 # Number of seconds simulated -sim_ticks 2100480012 # Number of ticks simulated +sim_seconds 0.378869 # Number of seconds simulated +sim_ticks 378869140000 # Number of ticks simulated system.cpu.dcache.ReadReq_accesses 114514042 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 2845.396229 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 1845.396229 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_miss_latency 2584.255983 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 1584.255983 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_hits 114312810 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 572584774 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency 520035000 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_rate 0.001757 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_misses 201232 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_miss_latency 371352774 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency 318803000 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate 0.001757 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_misses 201232 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_accesses 39451321 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 3026.723012 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 2026.723012 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_miss_latency 2608.788455 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 1608.788455 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_hits 39197158 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 769281001 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 663057500 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_rate 0.006442 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_misses 254163 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_miss_latency 515118001 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 408894500 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_rate 0.006442 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_misses 254163 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked @@ -37,29 +37,29 @@ system.cpu.dcache.blocked_cycles_no_mshrs 0 # n system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.demand_accesses 153965363 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 2946.597514 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 1946.597514 # average overall mshr miss latency +system.cpu.dcache.demand_avg_miss_latency 2597.947935 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 1597.947935 # average overall mshr miss latency system.cpu.dcache.demand_hits 153509968 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 1341865775 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency 1183092500 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_rate 0.002958 # miss rate for demand accesses system.cpu.dcache.demand_misses 455395 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 886470775 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 727697500 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_rate 0.002958 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_misses 455395 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.overall_accesses 153965363 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 2946.597514 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 1946.597514 # average overall mshr miss latency +system.cpu.dcache.overall_avg_miss_latency 2597.947935 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 1597.947935 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.cpu.dcache.overall_hits 153509968 # number of overall hits -system.cpu.dcache.overall_miss_latency 1341865775 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency 1183092500 # number of overall miss cycles system.cpu.dcache.overall_miss_rate 0.002958 # miss rate for overall accesses system.cpu.dcache.overall_misses 455395 # number of overall misses system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 886470775 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 727697500 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_rate 0.002958 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_misses 455395 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -76,18 +76,18 @@ system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.dcache.replacements 451299 # number of replacements system.cpu.dcache.sampled_refs 455395 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 4053.427393 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 4095.423304 # Cycle average of tags in use system.cpu.dcache.total_refs 153509968 # Total number of references to valid blocks. -system.cpu.dcache.warmup_cycle 33693000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.warmup_cycle 102411000 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 325723 # number of writebacks system.cpu.icache.ReadReq_accesses 601856966 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 4085.659119 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 3085.659119 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_miss_latency 3746.540881 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 2746.540881 # average ReadReq mshr miss latency system.cpu.icache.ReadReq_hits 601856171 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 3248099 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency 2978500 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_rate 0.000001 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_misses 795 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_miss_latency 2453099 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency 2183500 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate 0.000001 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_misses 795 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked @@ -99,29 +99,29 @@ system.cpu.icache.blocked_cycles_no_mshrs 0 # n system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.demand_accesses 601856966 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 4085.659119 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 3085.659119 # average overall mshr miss latency +system.cpu.icache.demand_avg_miss_latency 3746.540881 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 2746.540881 # average overall mshr miss latency system.cpu.icache.demand_hits 601856171 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 3248099 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency 2978500 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_rate 0.000001 # miss rate for demand accesses system.cpu.icache.demand_misses 795 # number of demand (read+write) misses system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 2453099 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 2183500 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_rate 0.000001 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_misses 795 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.overall_accesses 601856966 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 4085.659119 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 3085.659119 # average overall mshr miss latency +system.cpu.icache.overall_avg_miss_latency 3746.540881 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 2746.540881 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.cpu.icache.overall_hits 601856171 # number of overall hits -system.cpu.icache.overall_miss_latency 3248099 # number of overall miss cycles +system.cpu.icache.overall_miss_latency 2978500 # number of overall miss cycles system.cpu.icache.overall_miss_rate 0.000001 # miss rate for overall accesses system.cpu.icache.overall_misses 795 # number of overall misses system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 2453099 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 2183500 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_rate 0.000001 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_misses 795 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -138,23 +138,23 @@ system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.icache.replacements 24 # number of replacements system.cpu.icache.sampled_refs 795 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 642.094524 # Cycle average of tags in use +system.cpu.icache.tagsinuse 674.110982 # Cycle average of tags in use system.cpu.icache.total_refs 601856171 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.l2cache.ReadReq_accesses 456190 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 3251.348149 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1946.946471 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency 2564.564334 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1563.181738 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_hits 430092 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 84853684 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency 66930000 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_rate 0.057209 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_misses 26098 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 50811409 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency 40795917 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate 0.057209 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_misses 26098 # number of ReadReq MSHR misses -system.cpu.l2cache.WriteReqNoAck|Writeback_accesses 325723 # number of WriteReqNoAck|Writeback accesses(hits+misses) -system.cpu.l2cache.WriteReqNoAck|Writeback_hits 325723 # number of WriteReqNoAck|Writeback hits +system.cpu.l2cache.Writeback_accesses 325723 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_hits 325723 # number of Writeback hits system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked system.cpu.l2cache.avg_refs 28.960648 # Average number of references to valid blocks. @@ -164,29 +164,29 @@ system.cpu.l2cache.blocked_cycles_no_mshrs 0 # system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.demand_accesses 456190 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 3251.348149 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 1946.946471 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_miss_latency 2564.564334 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 1563.181738 # average overall mshr miss latency system.cpu.l2cache.demand_hits 430092 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 84853684 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency 66930000 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_rate 0.057209 # miss rate for demand accesses system.cpu.l2cache.demand_misses 26098 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 50811409 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 40795917 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_rate 0.057209 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_misses 26098 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.overall_accesses 781913 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 3251.348149 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 1946.946471 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_miss_latency 2564.564334 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 1563.181738 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.cpu.l2cache.overall_hits 755815 # number of overall hits -system.cpu.l2cache.overall_miss_latency 84853684 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency 66930000 # number of overall miss cycles system.cpu.l2cache.overall_miss_rate 0.033377 # miss rate for overall accesses system.cpu.l2cache.overall_misses 26098 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 50811409 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 40795917 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_rate 0.033377 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_misses 26098 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -203,12 +203,12 @@ system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.l2cache.replacements 903 # number of replacements system.cpu.l2cache.sampled_refs 26098 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 24085.007455 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 24878.910085 # Cycle average of tags in use system.cpu.l2cache.total_refs 755815 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 883 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 2100480012 # number of cpu cycles simulated +system.cpu.numCycles 378869140000 # number of cpu cycles simulated system.cpu.num_insts 601856965 # Number of instructions executed system.cpu.num_refs 154862034 # Number of memory references system.cpu.workload.PROG:num_syscalls 17 # Number of system calls diff --git a/tests/long/00.gzip/ref/alpha/tru64/simple-timing/stderr b/tests/long/00.gzip/ref/alpha/tru64/simple-timing/stderr index 87866a2a5..f33d007a7 100644 --- a/tests/long/00.gzip/ref/alpha/tru64/simple-timing/stderr +++ b/tests/long/00.gzip/ref/alpha/tru64/simple-timing/stderr @@ -1 +1,2 @@ warn: Entering event queue @ 0. Starting simulation... +warn: Increasing stack size by one page. |