Bus: Update the stats for the recent bus fix.

--HG--
extra : convert_revision : dc29f7b5e6fa30a50305193cb0e5aed942f7e407

3 files changed, 52 insertions, 50 deletions

diff --git a/tests/long/00.gzip/ref/alpha/tru64/simple-timing/config.ini b/tests/long/00.gzip/ref/alpha/tru64/simple-timing/config.ini
index b25116443..87443a024 100644
--- a/tests/long/00.gzip/ref/alpha/tru64/simple-timing/config.ini
+++ b/tests/long/00.gzip/ref/alpha/tru64/simple-timing/config.ini
@@ -152,6 +152,7 @@ type=Bus
 block_size=64
 bus_id=0
 clock=1000
+header_cycles=1
 responder_set=false
 width=64
 port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
@@ -181,6 +182,7 @@ type=Bus
 block_size=64
 bus_id=0
 clock=1000
+header_cycles=1
 responder_set=false
 width=64
 port=system.physmem.port[0] system.cpu.l2cache.mem_side
diff --git a/tests/long/00.gzip/ref/alpha/tru64/simple-timing/m5stats.txt b/tests/long/00.gzip/ref/alpha/tru64/simple-timing/m5stats.txt
index 1a22ca151..7a8a25a24 100644
--- a/tests/long/00.gzip/ref/alpha/tru64/simple-timing/m5stats.txt
+++ b/tests/long/00.gzip/ref/alpha/tru64/simple-timing/m5stats.txt
@@ -1,31 +1,31 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                 991240                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 177788                       # Number of bytes of host memory used
-host_seconds                                   607.18                       # Real time elapsed on the host
-host_tick_rate                             1262504824                       # Simulator tick rate (ticks/s)
+host_inst_rate                                1122189                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 222560                       # Number of bytes of host memory used
+host_seconds                                   536.32                       # Real time elapsed on the host
+host_tick_rate                             1430957420                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                   601856964                       # Number of instructions simulated
-sim_seconds                                  0.766562                       # Number of seconds simulated
-sim_ticks                                766562460000                       # Number of ticks simulated
+sim_seconds                                  0.767457                       # Number of seconds simulated
+sim_ticks                                767457055000                       # Number of ticks simulated
 system.cpu.dcache.ReadReq_accesses          114514042                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_avg_miss_latency 15027.272004                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 13027.272004                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency 16196.211338                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 13196.211338                       # average ReadReq mshr miss latency
 system.cpu.dcache.ReadReq_hits              114312810                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_latency     3023968000                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency     3259196000                       # number of ReadReq miss cycles
 system.cpu.dcache.ReadReq_miss_rate          0.001757                       # miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_misses               201232                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_mshr_miss_latency   2621504000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency   2655500000                       # number of ReadReq MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate     0.001757                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_mshr_misses          201232                       # number of ReadReq MSHR misses
 system.cpu.dcache.WriteReq_accesses          39451321                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_avg_miss_latency        25000                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency        23000                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency 26999.984797                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 23999.984797                       # average WriteReq mshr miss latency
 system.cpu.dcache.WriteReq_hits              39122430                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_miss_latency    8222275000                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency    8880052000                       # number of WriteReq miss cycles
 system.cpu.dcache.WriteReq_miss_rate         0.008337                       # miss rate for WriteReq accesses
 system.cpu.dcache.WriteReq_misses              328891                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_mshr_miss_latency   7564493000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency   7893379000                       # number of WriteReq MSHR miss cycles
 system.cpu.dcache.WriteReq_mshr_miss_rate     0.008337                       # mshr miss rate for WriteReq accesses
 system.cpu.dcache.WriteReq_mshr_misses         328891                       # number of WriteReq MSHR misses
 system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0>                       # average number of cycles each access was blocked
@@ -37,29 +37,29 @@ system.cpu.dcache.blocked_cycles_no_mshrs            0                       # n
 system.cpu.dcache.blocked_cycles_no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
 system.cpu.dcache.demand_accesses           153965363                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency 21214.403072                       # average overall miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 19214.403072                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_miss_latency 22898.927230                       # average overall miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 19898.927230                       # average overall mshr miss latency
 system.cpu.dcache.demand_hits               153435240                       # number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency     11246243000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency     12139248000                       # number of demand (read+write) miss cycles
 system.cpu.dcache.demand_miss_rate           0.003443                       # miss rate for demand accesses
 system.cpu.dcache.demand_misses                530123                       # number of demand (read+write) misses
 system.cpu.dcache.demand_mshr_hits                  0                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_miss_latency  10185997000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency  10548879000                       # number of demand (read+write) MSHR miss cycles
 system.cpu.dcache.demand_mshr_miss_rate      0.003443                       # mshr miss rate for demand accesses
 system.cpu.dcache.demand_mshr_misses           530123                       # number of demand (read+write) MSHR misses
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.dcache.overall_accesses          153965363                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_avg_miss_latency 21214.403072                       # average overall miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 19214.403072                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_miss_latency 22898.927230                       # average overall miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 19898.927230                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0>                       # average overall mshr uncacheable latency
 system.cpu.dcache.overall_hits              153435240                       # number of overall hits
-system.cpu.dcache.overall_miss_latency    11246243000                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency    12139248000                       # number of overall miss cycles
 system.cpu.dcache.overall_miss_rate          0.003443                       # miss rate for overall accesses
 system.cpu.dcache.overall_misses               530123                       # number of overall misses
 system.cpu.dcache.overall_mshr_hits                 0                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_miss_latency  10185997000                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency  10548879000                       # number of overall MSHR miss cycles
 system.cpu.dcache.overall_mshr_miss_rate     0.003443                       # mshr miss rate for overall accesses
 system.cpu.dcache.overall_mshr_misses          530123                       # number of overall MSHR misses
 system.cpu.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
@@ -76,9 +76,9 @@ system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss            0
 system.cpu.dcache.replacements                 451299                       # number of replacements
 system.cpu.dcache.sampled_refs                 455395                       # Sample count of references to valid blocks.
 system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse               4094.968634                       # Cycle average of tags in use
+system.cpu.dcache.tagsinuse               4094.918042                       # Cycle average of tags in use
 system.cpu.dcache.total_refs                153509968                       # Total number of references to valid blocks.
-system.cpu.dcache.warmup_cycle              342269000                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.warmup_cycle              357644000                       # Cycle when the warmup percentage was hit.
 system.cpu.dcache.writebacks                   325723                       # number of writebacks
 system.cpu.dtb.accesses                     153970296                       # DTB accesses
 system.cpu.dtb.acv                                  0                       # DTB access violations
@@ -93,13 +93,13 @@ system.cpu.dtb.write_acv                            0                       # DT
 system.cpu.dtb.write_hits                    39451321                       # DTB write hits
 system.cpu.dtb.write_misses                      2302                       # DTB write misses
 system.cpu.icache.ReadReq_accesses          601861898                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_avg_miss_latency        25000                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency        23000                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_miss_latency        27000                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency        24000                       # average ReadReq mshr miss latency
 system.cpu.icache.ReadReq_hits              601861103                       # number of ReadReq hits
-system.cpu.icache.ReadReq_miss_latency       19875000                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency       21465000                       # number of ReadReq miss cycles
 system.cpu.icache.ReadReq_miss_rate          0.000001                       # miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_misses                  795                       # number of ReadReq misses
-system.cpu.icache.ReadReq_mshr_miss_latency     18285000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency     19080000                       # number of ReadReq MSHR miss cycles
 system.cpu.icache.ReadReq_mshr_miss_rate     0.000001                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_mshr_misses             795                       # number of ReadReq MSHR misses
 system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0>                       # average number of cycles each access was blocked
@@ -111,29 +111,29 @@ system.cpu.icache.blocked_cycles_no_mshrs            0                       # n
 system.cpu.icache.blocked_cycles_no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
 system.cpu.icache.demand_accesses           601861898                       # number of demand (read+write) accesses
-system.cpu.icache.demand_avg_miss_latency        25000                       # average overall miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency        23000                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_miss_latency        27000                       # average overall miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency        24000                       # average overall mshr miss latency
 system.cpu.icache.demand_hits               601861103                       # number of demand (read+write) hits
-system.cpu.icache.demand_miss_latency        19875000                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency        21465000                       # number of demand (read+write) miss cycles
 system.cpu.icache.demand_miss_rate           0.000001                       # miss rate for demand accesses
 system.cpu.icache.demand_misses                   795                       # number of demand (read+write) misses
 system.cpu.icache.demand_mshr_hits                  0                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_miss_latency     18285000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency     19080000                       # number of demand (read+write) MSHR miss cycles
 system.cpu.icache.demand_mshr_miss_rate      0.000001                       # mshr miss rate for demand accesses
 system.cpu.icache.demand_mshr_misses              795                       # number of demand (read+write) MSHR misses
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.icache.overall_accesses          601861898                       # number of overall (read+write) accesses
-system.cpu.icache.overall_avg_miss_latency        25000                       # average overall miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency        23000                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_miss_latency        27000                       # average overall miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency        24000                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0>                       # average overall mshr uncacheable latency
 system.cpu.icache.overall_hits              601861103                       # number of overall hits
-system.cpu.icache.overall_miss_latency       19875000                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency       21465000                       # number of overall miss cycles
 system.cpu.icache.overall_miss_rate          0.000001                       # miss rate for overall accesses
 system.cpu.icache.overall_misses                  795                       # number of overall misses
 system.cpu.icache.overall_mshr_hits                 0                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_miss_latency     18285000                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency     19080000                       # number of overall MSHR miss cycles
 system.cpu.icache.overall_mshr_miss_rate     0.000001                       # mshr miss rate for overall accesses
 system.cpu.icache.overall_mshr_misses             795                       # number of overall MSHR misses
 system.cpu.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
@@ -150,7 +150,7 @@ system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss            0
 system.cpu.icache.replacements                     24                       # number of replacements
 system.cpu.icache.sampled_refs                    795                       # Sample count of references to valid blocks.
 system.cpu.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.tagsinuse                673.730766                       # Cycle average of tags in use
+system.cpu.icache.tagsinuse                673.689179                       # Cycle average of tags in use
 system.cpu.icache.total_refs                601861103                       # Total number of references to valid blocks.
 system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
 system.cpu.icache.writebacks                        0                       # number of writebacks
@@ -160,28 +160,28 @@ system.cpu.itb.acv                                  0                       # IT
 system.cpu.itb.hits                         601861898                       # ITB hits
 system.cpu.itb.misses                              20                       # ITB misses
 system.cpu.l2cache.ReadExReq_accesses          254163                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_avg_miss_latency        22000                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency        23000                       # average ReadExReq miss latency
 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency        11000                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_miss_latency   5591586000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency   5845749000                       # number of ReadExReq miss cycles
 system.cpu.l2cache.ReadExReq_miss_rate              1                       # miss rate for ReadExReq accesses
 system.cpu.l2cache.ReadExReq_misses            254163                       # number of ReadExReq misses
 system.cpu.l2cache.ReadExReq_mshr_miss_latency   2795793000                       # number of ReadExReq MSHR miss cycles
 system.cpu.l2cache.ReadExReq_mshr_miss_rate            1                       # mshr miss rate for ReadExReq accesses
 system.cpu.l2cache.ReadExReq_mshr_misses       254163                       # number of ReadExReq MSHR misses
 system.cpu.l2cache.ReadReq_accesses            202027                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_avg_miss_latency        22000                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency        23000                       # average ReadReq miss latency
 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency        11000                       # average ReadReq mshr miss latency
 system.cpu.l2cache.ReadReq_hits                167236                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_miss_latency     765402000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency     800193000                       # number of ReadReq miss cycles
 system.cpu.l2cache.ReadReq_miss_rate         0.172210                       # miss rate for ReadReq accesses
 system.cpu.l2cache.ReadReq_misses               34791                       # number of ReadReq misses
 system.cpu.l2cache.ReadReq_mshr_miss_latency    382701000                       # number of ReadReq MSHR miss cycles
 system.cpu.l2cache.ReadReq_mshr_miss_rate     0.172210                       # mshr miss rate for ReadReq accesses
 system.cpu.l2cache.ReadReq_mshr_misses          34791                       # number of ReadReq MSHR misses
 system.cpu.l2cache.UpgradeReq_accesses          74728                       # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_avg_miss_latency 21998.527995                       # average UpgradeReq miss latency
+system.cpu.l2cache.UpgradeReq_avg_miss_latency 22998.461086                       # average UpgradeReq miss latency
 system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency        11000                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_miss_latency   1643906000                       # number of UpgradeReq miss cycles
+system.cpu.l2cache.UpgradeReq_miss_latency   1718629000                       # number of UpgradeReq miss cycles
 system.cpu.l2cache.UpgradeReq_miss_rate             1                       # miss rate for UpgradeReq accesses
 system.cpu.l2cache.UpgradeReq_misses            74728                       # number of UpgradeReq misses
 system.cpu.l2cache.UpgradeReq_mshr_miss_latency    822008000                       # number of UpgradeReq MSHR miss cycles
@@ -198,10 +198,10 @@ system.cpu.l2cache.blocked_cycles_no_mshrs            0                       #
 system.cpu.l2cache.blocked_cycles_no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
 system.cpu.l2cache.demand_accesses             456190                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_avg_miss_latency        22000                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency        23000                       # average overall miss latency
 system.cpu.l2cache.demand_avg_mshr_miss_latency        11000                       # average overall mshr miss latency
 system.cpu.l2cache.demand_hits                 167236                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_miss_latency     6356988000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency     6645942000                       # number of demand (read+write) miss cycles
 system.cpu.l2cache.demand_miss_rate          0.633407                       # miss rate for demand accesses
 system.cpu.l2cache.demand_misses               288954                       # number of demand (read+write) misses
 system.cpu.l2cache.demand_mshr_hits                 0                       # number of demand (read+write) MSHR hits
@@ -212,11 +212,11 @@ system.cpu.l2cache.fast_writes                      0                       # nu
 system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu.l2cache.overall_accesses            456190                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_avg_miss_latency        22000                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency        23000                       # average overall miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency        11000                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0>                       # average overall mshr uncacheable latency
 system.cpu.l2cache.overall_hits                167236                       # number of overall hits
-system.cpu.l2cache.overall_miss_latency    6356988000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency    6645942000                       # number of overall miss cycles
 system.cpu.l2cache.overall_miss_rate         0.633407                       # miss rate for overall accesses
 system.cpu.l2cache.overall_misses              288954                       # number of overall misses
 system.cpu.l2cache.overall_mshr_hits                0                       # number of overall MSHR hits
@@ -237,12 +237,12 @@ system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss            0
 system.cpu.l2cache.replacements                 84513                       # number of replacements
 system.cpu.l2cache.sampled_refs                100134                       # Sample count of references to valid blocks.
 system.cpu.l2cache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.l2cache.tagsinuse             16358.690190                       # Cycle average of tags in use
+system.cpu.l2cache.tagsinuse             16357.683393                       # Cycle average of tags in use
 system.cpu.l2cache.total_refs                  352458                       # Total number of references to valid blocks.
 system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
 system.cpu.l2cache.writebacks                   63194                       # number of writebacks
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
-system.cpu.numCycles                       1533124920                       # number of cpu cycles simulated
+system.cpu.numCycles                       1534914110                       # number of cpu cycles simulated
 system.cpu.num_insts                        601856964                       # Number of instructions executed
 system.cpu.num_refs                         154866966                       # Number of memory references
 system.cpu.workload.PROG:num_syscalls              17                       # Number of system calls
diff --git a/tests/long/00.gzip/ref/alpha/tru64/simple-timing/stderr b/tests/long/00.gzip/ref/alpha/tru64/simple-timing/stderr
index 5992f7131..598fc86c0 100644
--- a/tests/long/00.gzip/ref/alpha/tru64/simple-timing/stderr
+++ b/tests/long/00.gzip/ref/alpha/tru64/simple-timing/stderr
@@ -1,3 +1,3 @@
-0: system.remote_gdb.listener: listening for remote gdb on port 7000
+0: system.remote_gdb.listener: listening for remote gdb on port 7006
 warn: Entering event queue @ 0.  Starting simulation...
 warn: Increasing stack size by one page.