diff options
| author | Ali Saidi <saidi@eecs.umich.edu> | 2007-05-15 19:25:35 -0400 |
|---|---|---|
| committer | Ali Saidi <saidi@eecs.umich.edu> | 2007-05-15 19:25:35 -0400 |
| commit | b85690e239616b703881b7734b0559f61f9eb75e (patch) | |
| tree | f144325bc982177a8ff0d87ba87cc9e840bfb301 /tests/long/00.gzip/ref/alpha/tru64 | |
| parent | c30e615689148c6e5ecd06e86069cba716dec5e0 (diff) | |
| download | gem5-b85690e239616b703881b7734b0559f61f9eb75e.tar.xz | |
update all the regresstion tests for release
--HG--
extra : convert_revision : 47e420b5b27e196a6e7a6424540923623bb3c4d2
Diffstat (limited to 'tests/long/00.gzip/ref/alpha/tru64')
9 files changed, 353 insertions, 355 deletions
diff --git a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/config.ini b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/config.ini index 2192c0d45..4de44cbb3 100644 --- a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/config.ini +++ b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/config.ini @@ -91,8 +91,7 @@ block_size=64 compressed_bus=false compression_latency=0 hash_delay=1 -hit_latency=1 -latency=1 +latency=1000 lifo=false max_miss_count=0 mshrs=10 @@ -267,8 +266,7 @@ block_size=64 compressed_bus=false compression_latency=0 hash_delay=1 -hit_latency=1 -latency=1 +latency=1000 lifo=false max_miss_count=0 mshrs=10 @@ -306,8 +304,7 @@ block_size=64 compressed_bus=false compression_latency=0 hash_delay=1 -hit_latency=1 -latency=1 +latency=1000 lifo=false max_miss_count=0 mshrs=10 @@ -339,6 +336,7 @@ mem_side=system.membus.port[1] [system.cpu.toL2Bus] type=Bus +block_size=64 bus_id=0 clock=1000 responder_set=false @@ -363,6 +361,7 @@ uid=100 [system.membus] type=Bus +block_size=64 bus_id=0 clock=1000 responder_set=false diff --git a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/config.out b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/config.out index 4c50c2a46..24d41aaa7 100644 --- a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/config.out +++ b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/config.out @@ -20,6 +20,7 @@ bus_id=0 clock=1000 width=64 responder_set=false +block_size=64 [system.cpu.workload] type=LiveProcess @@ -249,7 +250,7 @@ type=BaseCache size=131072 assoc=2 block_size=64 -latency=1 +latency=1000 mshrs=10 tgts_per_mshr=20 write_buffers=8 @@ -280,14 +281,13 @@ prefetch_policy=none prefetch_cache_check_push=true prefetch_use_cpu_id=true prefetch_data_accesses_only=false -hit_latency=1 [system.cpu.dcache] type=BaseCache size=262144 assoc=2 block_size=64 -latency=1 +latency=1000 mshrs=10 tgts_per_mshr=20 write_buffers=8 @@ -318,14 +318,13 @@ prefetch_policy=none prefetch_cache_check_push=true prefetch_use_cpu_id=true prefetch_data_accesses_only=false -hit_latency=1 [system.cpu.l2cache] type=BaseCache size=2097152 assoc=2 block_size=64 -latency=1 +latency=1000 mshrs=10 tgts_per_mshr=5 write_buffers=8 @@ -356,7 +355,6 @@ prefetch_policy=none prefetch_cache_check_push=true prefetch_use_cpu_id=true prefetch_data_accesses_only=false -hit_latency=1 [system.cpu.toL2Bus] type=Bus @@ -364,4 +362,5 @@ bus_id=0 clock=1000 width=64 responder_set=false +block_size=64 diff --git a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/m5stats.txt b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/m5stats.txt index 7e02db19e..21eca8681 100644 --- a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/m5stats.txt +++ b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/m5stats.txt @@ -1,40 +1,40 @@ ---------- Begin Simulation Statistics ---------- global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -global.BPredUnit.BTBHits 74294088 # Number of BTB hits -global.BPredUnit.BTBLookups 83217138 # Number of BTB lookups -global.BPredUnit.RASInCorrect 175 # Number of incorrect RAS predictions. -global.BPredUnit.condIncorrect 4320797 # Number of conditional branches incorrect -global.BPredUnit.condPredicted 79655810 # Number of conditional branches predicted -global.BPredUnit.lookups 86600861 # Number of BP lookups -global.BPredUnit.usedRAS 1992384 # Number of times the RAS was used to get a target. -host_inst_rate 121760 # Simulator instruction rate (inst/s) -host_mem_usage 154560 # Number of bytes of host memory used -host_seconds 4644.82 # Real time elapsed on the host -host_tick_rate 28265671 # Simulator tick rate (ticks/s) -memdepunit.memDep.conflictingLoads 20253948 # Number of conflicting loads. -memdepunit.memDep.conflictingStores 12668807 # Number of conflicting stores. -memdepunit.memDep.insertedLoads 134508955 # Number of loads inserted to the mem dependence unit. -memdepunit.memDep.insertedStores 44216516 # Number of stores inserted to the mem dependence unit. +global.BPredUnit.BTBHits 65796417 # Number of BTB hits +global.BPredUnit.BTBLookups 73152793 # Number of BTB lookups +global.BPredUnit.RASInCorrect 162 # Number of incorrect RAS predictions. +global.BPredUnit.condIncorrect 4224786 # Number of conditional branches incorrect +global.BPredUnit.condPredicted 70143727 # Number of conditional branches predicted +global.BPredUnit.lookups 75959317 # Number of BP lookups +global.BPredUnit.usedRAS 1707904 # Number of times the RAS was used to get a target. +host_inst_rate 95235 # Simulator instruction rate (inst/s) +host_mem_usage 154544 # Number of bytes of host memory used +host_seconds 5938.47 # Real time elapsed on the host +host_tick_rate 31305923 # Simulator tick rate (ticks/s) +memdepunit.memDep.conflictingLoads 11533351 # Number of conflicting loads. +memdepunit.memDep.conflictingStores 9283325 # Number of conflicting stores. +memdepunit.memDep.insertedLoads 125815870 # Number of loads inserted to the mem dependence unit. +memdepunit.memDep.insertedStores 42503953 # Number of stores inserted to the mem dependence unit. sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 565552443 # Number of instructions simulated -sim_seconds 0.131289 # Number of seconds simulated -sim_ticks 131288904500 # Number of ticks simulated +sim_seconds 0.185909 # Number of seconds simulated +sim_ticks 185909249000 # Number of ticks simulated system.cpu.commit.COM:branches 62547159 # Number of branches committed -system.cpu.commit.COM:bw_lim_events 25836005 # number cycles where commit BW limit reached +system.cpu.commit.COM:bw_lim_events 21750592 # number cycles where commit BW limit reached system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle.samples 248547939 +system.cpu.commit.COM:committed_per_cycle.samples 363164843 system.cpu.commit.COM:committed_per_cycle.min_value 0 - 0 64112537 2579.48% - 1 73997996 2977.21% - 2 29649485 1192.91% - 3 7413919 298.29% - 4 16299890 655.80% - 5 20436719 822.24% - 6 3362671 135.29% - 7 7438717 299.29% - 8 25836005 1039.48% + 0 150226418 4136.59% + 1 99566964 2741.65% + 2 34056070 937.76% + 3 10333475 284.54% + 4 20301573 559.02% + 5 15829471 435.88% + 6 8882909 244.60% + 7 2217371 61.06% + 8 21750592 598.92% system.cpu.commit.COM:committed_per_cycle.max_value 8 system.cpu.commit.COM:committed_per_cycle.end_dist @@ -43,70 +43,70 @@ system.cpu.commit.COM:loads 115049510 # Nu system.cpu.commit.COM:membars 0 # Number of memory barriers committed system.cpu.commit.COM:refs 154862033 # Number of memory references committed system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.branchMispredicts 4320164 # The number of times a branch was mispredicted +system.cpu.commit.branchMispredicts 4224164 # The number of times a branch was mispredicted system.cpu.commit.commitCommittedInsts 601856963 # The number of committed instructions system.cpu.commit.commitNonSpecStalls 17 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.commitSquashedInsts 94497449 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 52370845 # The number of squashed insts skipped by commit system.cpu.committedInsts 565552443 # Number of Instructions Simulated system.cpu.committedInsts_total 565552443 # Number of Instructions Simulated -system.cpu.cpi 0.464286 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.464286 # CPI: Total CPI of All Threads -system.cpu.dcache.ReadReq_accesses 115538611 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 2723.249468 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2089.628248 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 114910502 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 1710497500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.005436 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 628109 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_hits 403470 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_miss_latency 469412000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.001944 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 224639 # number of ReadReq MSHR misses +system.cpu.cpi 0.657443 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.657443 # CPI: Total CPI of All Threads +system.cpu.dcache.ReadReq_accesses 115591547 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 3246.088003 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2434.144734 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 115095381 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 1610598500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.004292 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 496166 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_hits 273177 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_miss_latency 542787500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.001929 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_misses 222989 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_accesses 39451321 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 3076.718619 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 2314.396461 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 38683248 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 2363144500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.019469 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 768073 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_hits 511246 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_miss_latency 594399500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate 0.006510 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 256827 # number of WriteReq MSHR misses -system.cpu.dcache.avg_blocked_cycles_no_mshrs 539.249147 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles_no_targets 250 # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 319.012661 # Average number of references to valid blocks. -system.cpu.dcache.blocked_no_mshrs 1172 # number of cycles access was blocked -system.cpu.dcache.blocked_no_targets 4 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles_no_mshrs 632000 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles_no_targets 1000 # number of cycles access was blocked +system.cpu.dcache.WriteReq_avg_miss_latency 3474.707454 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 2824.359825 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 38691611 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 2639770000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.019257 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 759710 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_hits 502007 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_miss_latency 727846000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate 0.006532 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_misses 257703 # number of WriteReq MSHR misses +system.cpu.dcache.avg_blocked_cycles_no_mshrs 427.272727 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles_no_targets 0 # average number of cycles each access was blocked +system.cpu.dcache.avg_refs 319.928337 # Average number of references to valid blocks. +system.cpu.dcache.blocked_no_mshrs 1210 # number of cycles access was blocked +system.cpu.dcache.blocked_no_targets 2 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles_no_mshrs 517000 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 154989932 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 2917.701274 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 2209.525699 # average overall mshr miss latency -system.cpu.dcache.demand_hits 153593750 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 4073642000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.009008 # miss rate for demand accesses -system.cpu.dcache.demand_misses 1396182 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits 914716 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 1063811500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.003106 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 481466 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_accesses 155042868 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 3384.385481 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 2643.342307 # average overall mshr miss latency +system.cpu.dcache.demand_hits 153786992 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 4250368500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.008100 # miss rate for demand accesses +system.cpu.dcache.demand_misses 1255876 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits 775184 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency 1270633500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.003100 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses 480692 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.overall_accesses 154989932 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 2917.701274 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 2209.525699 # average overall mshr miss latency +system.cpu.dcache.overall_accesses 155042868 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 3384.385481 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 2643.342307 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 153593750 # number of overall hits -system.cpu.dcache.overall_miss_latency 4073642000 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.009008 # miss rate for overall accesses -system.cpu.dcache.overall_misses 1396182 # number of overall misses -system.cpu.dcache.overall_mshr_hits 914716 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 1063811500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.003106 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 481466 # number of overall MSHR misses +system.cpu.dcache.overall_hits 153786992 # number of overall hits +system.cpu.dcache.overall_miss_latency 4250368500 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.008100 # miss rate for overall accesses +system.cpu.dcache.overall_misses 1255876 # number of overall misses +system.cpu.dcache.overall_mshr_hits 775184 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency 1270633500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.003100 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses 480692 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -118,92 +118,92 @@ system.cpu.dcache.prefetcher.num_hwpf_issued 0 system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.dcache.replacements 477370 # number of replacements -system.cpu.dcache.sampled_refs 481466 # Sample count of references to valid blocks. +system.cpu.dcache.replacements 476596 # number of replacements +system.cpu.dcache.sampled_refs 480692 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 4095.510322 # Cycle average of tags in use -system.cpu.dcache.total_refs 153593750 # Total number of references to valid blocks. -system.cpu.dcache.warmup_cycle 24474000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.writebacks 338333 # number of writebacks -system.cpu.decode.DECODE:BlockedCycles 34835558 # Number of cycles decode is blocked -system.cpu.decode.DECODE:BranchMispred 676 # Number of times decode detected a branch misprediction -system.cpu.decode.DECODE:BranchResolved 4837262 # Number of times decode resolved a branch -system.cpu.decode.DECODE:DecodedInsts 747469994 # Number of instructions handled by decode -system.cpu.decode.DECODE:IdleCycles 87926948 # Number of cycles decode is idle -system.cpu.decode.DECODE:RunCycles 115162373 # Number of cycles decode is running -system.cpu.decode.DECODE:SquashCycles 14029871 # Number of cycles decode is squashing -system.cpu.decode.DECODE:SquashedInsts 2002 # Number of squashed instructions handled by decode -system.cpu.decode.DECODE:UnblockCycles 10623061 # Number of cycles decode is unblocking -system.cpu.fetch.Branches 86600861 # Number of branches that fetch encountered -system.cpu.fetch.CacheLines 72219408 # Number of cache lines fetched -system.cpu.fetch.Cycles 200341434 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.IcacheSquashes 435 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.Insts 760297798 # Number of instructions fetch has processed -system.cpu.fetch.SquashCycles 4883794 # Number of cycles fetch has spent squashing -system.cpu.fetch.branchRate 0.329810 # Number of branch fetches per cycle -system.cpu.fetch.icacheStallCycles 72219408 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.predictedBranches 76286472 # Number of branches that fetch has predicted taken -system.cpu.fetch.rate 2.895514 # Number of inst fetches per cycle +system.cpu.dcache.tagsinuse 4095.610639 # Cycle average of tags in use +system.cpu.dcache.total_refs 153786992 # Total number of references to valid blocks. +system.cpu.dcache.warmup_cycle 28323000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.writebacks 338024 # number of writebacks +system.cpu.decode.DECODE:BlockedCycles 44010110 # Number of cycles decode is blocked +system.cpu.decode.DECODE:BranchMispred 636 # Number of times decode detected a branch misprediction +system.cpu.decode.DECODE:BranchResolved 3910489 # Number of times decode resolved a branch +system.cpu.decode.DECODE:DecodedInsts 686828869 # Number of instructions handled by decode +system.cpu.decode.DECODE:IdleCycles 203536444 # Number of cycles decode is idle +system.cpu.decode.DECODE:RunCycles 106139742 # Number of cycles decode is running +system.cpu.decode.DECODE:SquashCycles 8653682 # Number of cycles decode is squashing +system.cpu.decode.DECODE:SquashedInsts 1958 # Number of squashed instructions handled by decode +system.cpu.decode.DECODE:UnblockCycles 9478548 # Number of cycles decode is unblocking +system.cpu.fetch.Branches 75959317 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 65390933 # Number of cache lines fetched +system.cpu.fetch.Cycles 182129217 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 2901518 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.Insts 693889852 # Number of instructions fetch has processed +system.cpu.fetch.SquashCycles 4411999 # Number of cycles fetch has spent squashing +system.cpu.fetch.branchRate 0.204291 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 65390933 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 67504321 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 1.866206 # Number of inst fetches per cycle system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist.samples 262577811 +system.cpu.fetch.rateDist.samples 371818526 system.cpu.fetch.rateDist.min_value 0 - 0 134455787 5120.61% - 1 11289278 429.94% - 2 12199345 464.60% - 3 11605085 441.97% - 4 7894720 300.66% - 5 3823699 145.62% - 6 3913283 149.03% - 7 3555410 135.40% - 8 73841204 2812.16% + 0 255080243 6860.34% + 1 9944321 267.45% + 2 12043396 323.91% + 3 10077209 271.02% + 4 7005486 188.41% + 5 3160802 85.01% + 6 3551742 95.52% + 7 3151910 84.77% + 8 67803417 1823.56% system.cpu.fetch.rateDist.max_value 8 system.cpu.fetch.rateDist.end_dist -system.cpu.icache.ReadReq_accesses 72219408 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 4241.833509 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 3311.810155 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 72218459 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 4025500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate 0.000013 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 949 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_hits 43 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_miss_latency 3000500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.000013 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 906 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_accesses 65390933 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 5347.983454 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 4573.991031 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 65389966 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 5171500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate 0.000015 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses 967 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_hits 75 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_miss_latency 4080000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.000014 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_misses 892 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.icache.avg_refs 79711.323400 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 73307.136771 # Average number of references to valid blocks. system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 72219408 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 4241.833509 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 3311.810155 # average overall mshr miss latency -system.cpu.icache.demand_hits 72218459 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 4025500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.000013 # miss rate for demand accesses -system.cpu.icache.demand_misses 949 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_hits 43 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 3000500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate 0.000013 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 906 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_accesses 65390933 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 5347.983454 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 4573.991031 # average overall mshr miss latency +system.cpu.icache.demand_hits 65389966 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 5171500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate 0.000015 # miss rate for demand accesses +system.cpu.icache.demand_misses 967 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_hits 75 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_miss_latency 4080000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate 0.000014 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_misses 892 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.overall_accesses 72219408 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 4241.833509 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 3311.810155 # average overall mshr miss latency +system.cpu.icache.overall_accesses 65390933 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 5347.983454 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 4573.991031 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 72218459 # number of overall hits -system.cpu.icache.overall_miss_latency 4025500 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.000013 # miss rate for overall accesses -system.cpu.icache.overall_misses 949 # number of overall misses -system.cpu.icache.overall_mshr_hits 43 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 3000500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate 0.000013 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 906 # number of overall MSHR misses +system.cpu.icache.overall_hits 65389966 # number of overall hits +system.cpu.icache.overall_miss_latency 5171500 # number of overall miss cycles +system.cpu.icache.overall_miss_rate 0.000015 # miss rate for overall accesses +system.cpu.icache.overall_misses 967 # number of overall misses +system.cpu.icache.overall_mshr_hits 75 # number of overall MSHR hits +system.cpu.icache.overall_mshr_miss_latency 4080000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate 0.000014 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_misses 892 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -215,63 +215,63 @@ system.cpu.icache.prefetcher.num_hwpf_issued 0 system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.icache.replacements 34 # number of replacements -system.cpu.icache.sampled_refs 906 # Sample count of references to valid blocks. +system.cpu.icache.replacements 33 # number of replacements +system.cpu.icache.sampled_refs 892 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 774.513861 # Cycle average of tags in use -system.cpu.icache.total_refs 72218459 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 761.711791 # Cycle average of tags in use +system.cpu.icache.total_refs 65389966 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.idleCycles 997 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.iew.EXEC:branches 69153659 # Number of branches executed -system.cpu.iew.EXEC:nop 45896023 # number of nop insts executed -system.cpu.iew.EXEC:rate 2.341699 # Inst execution rate -system.cpu.iew.EXEC:refs 168426251 # number of memory reference insts executed -system.cpu.iew.EXEC:stores 41748280 # Number of stores executed +system.cpu.idleCycles 2468 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.iew.EXEC:branches 67136036 # Number of branches executed +system.cpu.iew.EXEC:nop 41949449 # number of nop insts executed +system.cpu.iew.EXEC:rate 1.608660 # Inst execution rate +system.cpu.iew.EXEC:refs 164353457 # number of memory reference insts executed +system.cpu.iew.EXEC:stores 41112797 # Number of stores executed system.cpu.iew.EXEC:swp 0 # number of swp insts executed -system.cpu.iew.WB:consumers 525987328 # num instructions consuming a value -system.cpu.iew.WB:count 611675009 # cumulative count of insts written-back -system.cpu.iew.WB:fanout 0.792003 # average fanout of values written-back +system.cpu.iew.WB:consumers 478961290 # num instructions consuming a value +system.cpu.iew.WB:count 594114153 # cumulative count of insts written-back +system.cpu.iew.WB:fanout 0.812310 # average fanout of values written-back system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.WB:producers 416583352 # num instructions producing a value -system.cpu.iew.WB:rate 2.329500 # insts written-back per cycle -system.cpu.iew.WB:sent 613682130 # cumulative count of insts sent to commit -system.cpu.iew.branchMispredicts 4878985 # Number of branch mispredicts detected at execute -system.cpu.iew.iewBlockCycles 11826 # Number of cycles IEW is blocking -system.cpu.iew.iewDispLoadInsts 134508955 # Number of dispatched load instructions -system.cpu.iew.iewDispNonSpecInsts 23 # Number of dispatched non-speculative instructions -system.cpu.iew.iewDispSquashedInsts 2507193 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispStoreInsts 44216516 # Number of dispatched store instructions -system.cpu.iew.iewDispatchedInsts 696353635 # Number of instructions dispatched to IQ -system.cpu.iew.iewExecLoadInsts 126677971 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 11034988 # Number of squashed instructions skipped in execute -system.cpu.iew.iewExecutedInsts 614878076 # Number of executed instructions -system.cpu.iew.iewIQFullEvents 14 # Number of times the IQ has become full, causing a stall +system.cpu.iew.WB:producers 389064913 # num instructions producing a value +system.cpu.iew.WB:rate 1.597861 # insts written-back per cycle +system.cpu.iew.WB:sent 594699658 # cumulative count of insts sent to commit +system.cpu.iew.branchMispredicts 4485637 # Number of branch mispredicts detected at execute +system.cpu.iew.iewBlockCycles 10981 # Number of cycles IEW is blocking +system.cpu.iew.iewDispLoadInsts 125815870 # Number of dispatched load instructions +system.cpu.iew.iewDispNonSpecInsts 22 # Number of dispatched non-speculative instructions +system.cpu.iew.iewDispSquashedInsts 6586227 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispStoreInsts 42503953 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 654225210 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts 123240660 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 4346710 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 598129643 # Number of executed instructions +system.cpu.iew.iewIQFullEvents 518 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewLSQFullEvents 1 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.iewSquashCycles 14029871 # Number of cycles IEW is squashing -system.cpu.iew.iewUnblockCycles 4036 # Number of cycles IEW is unblocking +system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 8653682 # Number of cycles IEW is squashing +system.cpu.iew.iewUnblockCycles 4417 # Number of cycles IEW is unblocking system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread.0.cacheBlocked 4056 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread.0.forwLoads 10594878 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread.0.ignoredResponses 23131 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread.0.cacheBlocked 2615 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread.0.forwLoads 7105932 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread.0.ignoredResponses 1847 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread.0.memOrderViolation 1076564 # Number of memory ordering violations -system.cpu.iew.lsq.thread.0.rescheduledLoads 5809 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread.0.squashedLoads 19459445 # Number of loads squashed -system.cpu.iew.lsq.thread.0.squashedStores 4403993 # Number of stores squashed -system.cpu.iew.memOrderViolationEvents 1076564 # Number of memory order violations -system.cpu.iew.predictedNotTakenIncorrect 574744 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.predictedTakenIncorrect 4304241 # Number of branches that were predicted taken incorrectly -system.cpu.ipc 2.153847 # IPC: Instructions Per Cycle -system.cpu.ipc_total 2.153847 # IPC: Total IPC of All Threads -system.cpu.iq.ISSUE:FU_type_0 625913064 # Type of FU issued +system.cpu.iew.lsq.thread.0.memOrderViolation 296430 # Number of memory ordering violations +system.cpu.iew.lsq.thread.0.rescheduledLoads 5860 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread.0.squashedLoads 10766360 # Number of loads squashed +system.cpu.iew.lsq.thread.0.squashedStores 2691430 # Number of stores squashed +system.cpu.iew.memOrderViolationEvents 296430 # Number of memory order violations +system.cpu.iew.predictedNotTakenIncorrect 519296 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 3966341 # Number of branches that were predicted taken incorrectly +system.cpu.ipc 1.521044 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.521044 # IPC: Total IPC of All Threads +system.cpu.iq.ISSUE:FU_type_0 602476353 # Type of FU issued system.cpu.iq.ISSUE:FU_type_0.start_dist (null) 0 0.00% # Type of FU issued - IntAlu 452893161 72.36% # Type of FU issued - IntMult 6537 0.00% # Type of FU issued + IntAlu 435905994 72.35% # Type of FU issued + IntMult 6492 0.00% # Type of FU issued IntDiv 0 0.00% # Type of FU issued FloatAdd 27 0.00% # Type of FU issued FloatCmp 5 0.00% # Type of FU issued @@ -279,17 +279,17 @@ system.cpu.iq.ISSUE:FU_type_0.start_dist FloatMult 4 0.00% # Type of FU issued FloatDiv 0 0.00% # Type of FU issued FloatSqrt 0 0.00% # Type of FU issued - MemRead 130507417 20.85% # Type of FU issued - MemWrite 42505908 6.79% # Type of FU issued + MemRead 124769613 20.71% # Type of FU issued + MemWrite 41794213 6.94% # Type of FU issued IprAccess 0 0.00% # Type of FU issued InstPrefetch 0 0.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0.end_dist -system.cpu.iq.ISSUE:fu_busy_cnt 6267821 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_rate 0.010014 # FU busy rate (busy events/executed inst) +system.cpu.iq.ISSUE:fu_busy_cnt 3485464 # FU busy when requested +system.cpu.iq.ISSUE:fu_busy_rate 0.005785 # FU busy rate (busy events/executed inst) system.cpu.iq.ISSUE:fu_full.start_dist (null) 0 0.00% # attempts to use FU when none available - IntAlu 5230779 83.45% # attempts to use FU when none available - IntMult 183 0.00% # attempts to use FU when none available + IntAlu 2980889 85.52% # attempts to use FU when none available + IntMult 104 0.00% # attempts to use FU when none available IntDiv 0 0.00% # attempts to use FU when none available FloatAdd 0 0.00% # attempts to use FU when none available FloatCmp 0 0.00% # attempts to use FU when none available @@ -297,80 +297,80 @@ system.cpu.iq.ISSUE:fu_full.start_dist FloatMult 0 0.00% # attempts to use FU when none available FloatDiv 0 0.00% # attempts to use FU when none available FloatSqrt 0 0.00% # attempts to use FU when none available - MemRead 663118 10.58% # attempts to use FU when none available - MemWrite 373741 5.96% # attempts to use FU when none available + MemRead 331227 9.50% # attempts to use FU when none available + MemWrite 173244 4.97% # attempts to use FU when none available IprAccess 0 0.00% # attempts to use FU when none available InstPrefetch 0 0.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full.end_dist system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle.samples 262577811 +system.cpu.iq.ISSUE:issued_per_cycle.samples 371818526 system.cpu.iq.ISSUE:issued_per_cycle.min_value 0 - 0 49543053 1886.80% - 1 42653619 1624.42% - 2 65996372 2513.40% - 3 28722982 1093.88% - 4 36210264 1379.03% - 5 20379063 776.12% - 6 16095665 612.99% - 7 2026950 77.19% - 8 949843 36.17% + 0 125625601 3378.68% + 1 89616652 2410.23% + 2 55904072 1503.53% + 3 46310572 1245.52% + 4 27240019 732.62% + 5 12675210 340.90% + 6 11517465 309.76% + 7 2752555 74.03% + 8 176380 4.74% system.cpu.iq.ISSUE:issued_per_cycle.max_value 8 system.cpu.iq.ISSUE:issued_per_cycle.end_dist -system.cpu.iq.ISSUE:rate 2.383724 # Inst issue rate -system.cpu.iq.iqInstsAdded 650457589 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqInstsIssued 625913064 # Number of instructions issued -system.cpu.iq.iqNonSpecInstsAdded 23 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqSquashedInstsExamined 83477196 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedInstsIssued 265708 # Number of squashed instructions issued -system.cpu.iq.iqSquashedNonSpecRemoved 6 # Number of squashed non-spec instructions that were removed -system.cpu.iq.iqSquashedOperandsExamined 44589775 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.l2cache.ReadReq_accesses 482372 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 5974.559204 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 2202.761362 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_hits 456056 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 157226500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.054555 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 26316 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 57967868 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.054555 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 26316 # number of ReadReq MSHR misses -system.cpu.l2cache.Writeback_accesses 338333 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_hits 338333 # number of Writeback hits +system.cpu.iq.ISSUE:rate 1.620351 # Inst issue rate +system.cpu.iq.iqInstsAdded 612275739 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 602476353 # Number of instructions issued +system.cpu.iq.iqNonSpecInstsAdded 22 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqSquashedInstsExamined 42659982 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsIssued 2623 # Number of squashed instructions issued +system.cpu.iq.iqSquashedNonSpecRemoved 5 # Number of squashed non-spec instructions that were removed +system.cpu.iq.iqSquashedOperandsExamined 21979774 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.l2cache.ReadReq_accesses 481584 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency 6174.721472 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 2416.099471 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_hits 455285 # number of ReadReq hits +system.cpu.l2cache.ReadReq_miss_latency 162389000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.054609 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 26299 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 63541000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.054609 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 26299 # number of ReadReq MSHR misses +system.cpu.l2cache.Writeback_accesses 338024 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_hits 338024 # number of Writeback hits system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 30.186541 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 30.164987 # Average number of references to valid blocks. system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 482372 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 5974.559204 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 2202.761362 # average overall mshr miss latency -system.cpu.l2cache.demand_hits 456056 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 157226500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.054555 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 26316 # number of demand (read+write) misses +system.cpu.l2cache.demand_accesses 481584 # number of demand (read+write) accesses +system.cpu.l2cache.demand_avg_miss_latency 6174.721472 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 2416.099471 # average overall mshr miss latency +system.cpu.l2cache.demand_hits 455285 # number of demand (read+write) hits +system.cpu.l2cache.demand_miss_latency 162389000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.054609 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 26299 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 57967868 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.054555 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 26316 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_miss_latency 63541000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.054609 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 26299 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.overall_accesses 820705 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 5974.559204 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 2202.761362 # average overall mshr miss latency +system.cpu.l2cache.overall_accesses 819608 # number of overall (read+write) accesses +system.cpu.l2cache.overall_avg_miss_latency 6174.721472 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 2416.099471 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu.l2cache.overall_hits 794389 # number of overall hits -system.cpu.l2cache.overall_miss_latency 157226500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.032065 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 26316 # number of overall misses +system.cpu.l2cache.overall_hits 793309 # number of overall hits +system.cpu.l2cache.overall_miss_latency 162389000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.032087 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 26299 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 57967868 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.032065 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 26316 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_miss_latency 63541000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.032087 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 26299 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -382,31 +382,31 @@ system.cpu.l2cache.prefetcher.num_hwpf_issued 0 system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.l2cache.replacements 932 # number of replacements -system.cpu.l2cache.sampled_refs 26316 # Sample count of references to valid blocks. +system.cpu.l2cache.replacements 931 # number of replacements +system.cpu.l2cache.sampled_refs 26299 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 25073.756706 # Cycle average of tags in use -system.cpu.l2cache.total_refs 794389 # Total number of references to valid blocks. +system.cpu.l2cache.tagsinuse 25071.267749 # Cycle average of tags in use +system.cpu.l2cache.total_refs 793309 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 904 # number of writebacks -system.cpu.numCycles 262577811 # number of cpu cycles simulated -system.cpu.rename.RENAME:BlockCycles 2682297 # Number of cycles rename is blocking +system.cpu.numCycles 371818526 # number of cpu cycles simulated +system.cpu.rename.RENAME:BlockCycles 11517489 # Number of cycles rename is blocking system.cpu.rename.RENAME:CommittedMaps 463854889 # Number of HB maps that are committed -system.cpu.rename.RENAME:IQFullEvents 30243185 # Number of times rename has blocked due to IQ full -system.cpu.rename.RENAME:IdleCycles 96498295 # Number of cycles rename is idle -system.cpu.rename.RENAME:LSQFullEvents 1942834 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RENAME:RenameLookups 952429183 # Number of register rename lookups that rename has made -system.cpu.rename.RENAME:RenamedInsts 727912324 # Number of instructions processed by rename -system.cpu.rename.RENAME:RenamedOperands 552445892 # Number of destination operands rename has renamed -system.cpu.rename.RENAME:RunCycles 117213862 # Number of cycles rename is running -system.cpu.rename.RENAME:SquashCycles 14029871 # Number of cycles rename is squashing -system.cpu.rename.RENAME:UnblockCycles 32153216 # Number of cycles rename is unblocking -system.cpu.rename.RENAME:UndoneMaps 88591003 # Number of HB maps that are undone due to squashing -system.cpu.rename.RENAME:serializeStallCycles 270 # count of cycles rename stalled for serializing inst -system.cpu.rename.RENAME:serializingInsts 33 # count of serializing insts renamed -system.cpu.rename.RENAME:skidInsts 50706382 # count of insts added to the skid buffer -system.cpu.rename.RENAME:tempSerializingInsts 31 # count of temporary serializing insts renamed -system.cpu.timesIdled 3 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.rename.RENAME:IQFullEvents 32462126 # Number of times rename has blocked due to IQ full +system.cpu.rename.RENAME:IdleCycles 206624315 # Number of cycles rename is idle +system.cpu.rename.RENAME:LSQFullEvents 21712 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RENAME:RenameLookups 889109667 # Number of register rename lookups that rename has made +system.cpu.rename.RENAME:RenamedInsts 674900294 # Number of instructions processed by rename +system.cpu.rename.RENAME:RenamedOperands 515718683 # Number of destination operands rename has renamed +system.cpu.rename.RENAME:RunCycles 111518348 # Number of cycles rename is running +system.cpu.rename.RENAME:SquashCycles 8653682 # Number of cycles rename is squashing +system.cpu.rename.RENAME:UnblockCycles 33504424 # Number of cycles rename is unblocking +system.cpu.rename.RENAME:UndoneMaps 51863794 # Number of HB maps that are undone due to squashing +system.cpu.rename.RENAME:serializeStallCycles 268 # count of cycles rename stalled for serializing inst +system.cpu.rename.RENAME:serializingInsts 26 # count of serializing insts renamed +system.cpu.rename.RENAME:skidInsts 59569309 # count of insts added to the skid buffer +system.cpu.rename.RENAME:tempSerializingInsts 24 # count of temporary serializing insts renamed +system.cpu.timesIdled 32 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.workload.PROG:num_syscalls 17 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/config.ini b/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/config.ini index 27aeb9034..e7acc71a6 100644 --- a/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/config.ini +++ b/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/config.ini @@ -48,6 +48,7 @@ uid=100 [system.membus] type=Bus +block_size=64 bus_id=0 clock=1000 responder_set=false diff --git a/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/config.out b/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/config.out index a8a9148d5..589507187 100644 --- a/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/config.out +++ b/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/config.out @@ -20,6 +20,7 @@ bus_id=0 clock=1000 width=64 responder_set=false +block_size=64 [system.cpu.workload] type=LiveProcess diff --git a/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/m5stats.txt b/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/m5stats.txt index 7c260dd71..5453dc099 100644 --- a/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/m5stats.txt +++ b/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/m5stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 964119 # Simulator instruction rate (inst/s) -host_mem_usage 148524 # Number of bytes of host memory used -host_seconds 624.26 # Real time elapsed on the host -host_tick_rate 482059313 # Simulator tick rate (ticks/s) +host_inst_rate 963880 # Simulator instruction rate (inst/s) +host_mem_usage 148548 # Number of bytes of host memory used +host_seconds 624.41 # Real time elapsed on the host +host_tick_rate 481939681 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 601856965 # Number of instructions simulated sim_seconds 0.300928 # Number of seconds simulated diff --git a/tests/long/00.gzip/ref/alpha/tru64/simple-timing/config.ini b/tests/long/00.gzip/ref/alpha/tru64/simple-timing/config.ini index f70ed5de3..f82815f7b 100644 --- a/tests/long/00.gzip/ref/alpha/tru64/simple-timing/config.ini +++ b/tests/long/00.gzip/ref/alpha/tru64/simple-timing/config.ini @@ -36,8 +36,7 @@ block_size=64 compressed_bus=false compression_latency=0 hash_delay=1 -hit_latency=1 -latency=1 +latency=1000 lifo=false max_miss_count=0 mshrs=10 @@ -75,8 +74,7 @@ block_size=64 compressed_bus=false compression_latency=0 hash_delay=1 -hit_latency=1 -latency=1 +latency=1000 lifo=false max_miss_count=0 mshrs=10 @@ -114,8 +112,7 @@ block_size=64 compressed_bus=false compression_latency=0 hash_delay=1 -hit_latency=1 -latency=1 +latency=10000 lifo=false max_miss_count=0 mshrs=10 @@ -147,6 +144,7 @@ mem_side=system.membus.port[1] [system.cpu.toL2Bus] type=Bus +block_size=64 bus_id=0 clock=1000 responder_set=false @@ -171,6 +169,7 @@ uid=100 [system.membus] type=Bus +block_size=64 bus_id=0 clock=1000 responder_set=false diff --git a/tests/long/00.gzip/ref/alpha/tru64/simple-timing/config.out b/tests/long/00.gzip/ref/alpha/tru64/simple-timing/config.out index d4c1bde6e..5cab10662 100644 --- a/tests/long/00.gzip/ref/alpha/tru64/simple-timing/config.out +++ b/tests/long/00.gzip/ref/alpha/tru64/simple-timing/config.out @@ -20,6 +20,7 @@ bus_id=0 clock=1000 width=64 responder_set=false +block_size=64 [system.cpu.workload] type=LiveProcess @@ -61,13 +62,14 @@ bus_id=0 clock=1000 width=64 responder_set=false +block_size=64 [system.cpu.icache] type=BaseCache size=131072 assoc=2 block_size=64 -latency=1 +latency=1000 mshrs=10 tgts_per_mshr=5 write_buffers=8 @@ -98,14 +100,13 @@ prefetch_policy=none prefetch_cache_check_push=true prefetch_use_cpu_id=true prefetch_data_accesses_only=false -hit_latency=1 [system.cpu.dcache] type=BaseCache size=262144 assoc=2 block_size=64 -latency=1 +latency=1000 mshrs=10 tgts_per_mshr=5 write_buffers=8 @@ -136,14 +137,13 @@ prefetch_policy=none prefetch_cache_check_push=true prefetch_use_cpu_id=true prefetch_data_accesses_only=false -hit_latency=1 [system.cpu.l2cache] type=BaseCache size=2097152 assoc=2 block_size=64 -latency=1 +latency=10000 mshrs=10 tgts_per_mshr=5 write_buffers=8 @@ -174,5 +174,4 @@ prefetch_policy=none prefetch_cache_check_push=true prefetch_use_cpu_id=true prefetch_data_accesses_only=false -hit_latency=1 diff --git a/tests/long/00.gzip/ref/alpha/tru64/simple-timing/m5stats.txt b/tests/long/00.gzip/ref/alpha/tru64/simple-timing/m5stats.txt index 5fbf59915..9d4ab211d 100644 --- a/tests/long/00.gzip/ref/alpha/tru64/simple-timing/m5stats.txt +++ b/tests/long/00.gzip/ref/alpha/tru64/simple-timing/m5stats.txt @@ -1,31 +1,31 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 642291 # Simulator instruction rate (inst/s) -host_mem_usage 153996 # Number of bytes of host memory used -host_seconds 937.05 # Real time elapsed on the host -host_tick_rate 404322160 # Simulator tick rate (ticks/s) +host_inst_rate 494073 # Simulator instruction rate (inst/s) +host_mem_usage 153964 # Number of bytes of host memory used +host_seconds 1218.16 # Real time elapsed on the host +host_tick_rate 624626994 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 601856965 # Number of instructions simulated -sim_seconds 0.378869 # Number of seconds simulated -sim_ticks 378869140000 # Number of ticks simulated +sim_seconds 0.760893 # Number of seconds simulated +sim_ticks 760892614000 # Number of ticks simulated system.cpu.dcache.ReadReq_accesses 114514042 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 2584.255983 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 1584.255983 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_miss_latency 12040.967639 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 11040.967639 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_hits 114312810 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 520035000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency 2423028000 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_rate 0.001757 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_misses 201232 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_miss_latency 318803000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency 2221796000 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate 0.001757 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_misses 201232 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_accesses 39451321 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 2608.788455 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 1608.788455 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_miss_latency 12166.766996 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 11166.766996 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_hits 39197158 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 663057500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 3092342000 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_rate 0.006442 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_misses 254163 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_miss_latency 408894500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 2838179000 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_rate 0.006442 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_misses 254163 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked @@ -37,29 +37,29 @@ system.cpu.dcache.blocked_cycles_no_mshrs 0 # n system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.demand_accesses 153965363 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 2597.947935 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 1597.947935 # average overall mshr miss latency +system.cpu.dcache.demand_avg_miss_latency 12111.178208 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 11111.178208 # average overall mshr miss latency system.cpu.dcache.demand_hits 153509968 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 1183092500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency 5515370000 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_rate 0.002958 # miss rate for demand accesses system.cpu.dcache.demand_misses 455395 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 727697500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 5059975000 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_rate 0.002958 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_misses 455395 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.overall_accesses 153965363 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 2597.947935 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 1597.947935 # average overall mshr miss latency +system.cpu.dcache.overall_avg_miss_latency 12111.178208 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 11111.178208 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.cpu.dcache.overall_hits 153509968 # number of overall hits -system.cpu.dcache.overall_miss_latency 1183092500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency 5515370000 # number of overall miss cycles system.cpu.dcache.overall_miss_rate 0.002958 # miss rate for overall accesses system.cpu.dcache.overall_misses 455395 # number of overall misses system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 727697500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 5059975000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_rate 0.002958 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_misses 455395 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -76,18 +76,18 @@ system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.dcache.replacements 451299 # number of replacements system.cpu.dcache.sampled_refs 455395 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 4095.423304 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 4095.250869 # Cycle average of tags in use system.cpu.dcache.total_refs 153509968 # Total number of references to valid blocks. -system.cpu.dcache.warmup_cycle 102411000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.warmup_cycle 257148000 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 325723 # number of writebacks system.cpu.icache.ReadReq_accesses 601856966 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 3746.540881 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 2746.540881 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_miss_latency 13969.811321 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 12969.811321 # average ReadReq mshr miss latency system.cpu.icache.ReadReq_hits 601856171 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 2978500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency 11106000 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_rate 0.000001 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_misses 795 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_miss_latency 2183500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency 10311000 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate 0.000001 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_misses 795 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked @@ -99,29 +99,29 @@ system.cpu.icache.blocked_cycles_no_mshrs 0 # n system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.demand_accesses 601856966 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 3746.540881 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 2746.540881 # average overall mshr miss latency +system.cpu.icache.demand_avg_miss_latency 13969.811321 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 12969.811321 # average overall mshr miss latency system.cpu.icache.demand_hits 601856171 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 2978500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency 11106000 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_rate 0.000001 # miss rate for demand accesses system.cpu.icache.demand_misses 795 # number of demand (read+write) misses system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 2183500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 10311000 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_rate 0.000001 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_misses 795 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.overall_accesses 601856966 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 3746.540881 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 2746.540881 # average overall mshr miss latency +system.cpu.icache.overall_avg_miss_latency 13969.811321 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 12969.811321 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.cpu.icache.overall_hits 601856171 # number of overall hits -system.cpu.icache.overall_miss_latency 2978500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency 11106000 # number of overall miss cycles system.cpu.icache.overall_miss_rate 0.000001 # miss rate for overall accesses system.cpu.icache.overall_misses 795 # number of overall misses system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 2183500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 10311000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_rate 0.000001 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_misses 795 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -138,19 +138,19 @@ system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.icache.replacements 24 # number of replacements system.cpu.icache.sampled_refs 795 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 674.110982 # Cycle average of tags in use +system.cpu.icache.tagsinuse 673.943506 # Cycle average of tags in use system.cpu.icache.total_refs 601856171 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.l2cache.ReadReq_accesses 456190 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 2564.564334 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1563.181738 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency 13000 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 11000 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_hits 430092 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 66930000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency 339274000 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_rate 0.057209 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_misses 26098 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 40795917 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency 287078000 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate 0.057209 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_misses 26098 # number of ReadReq MSHR misses system.cpu.l2cache.Writeback_accesses 325723 # number of Writeback accesses(hits+misses) @@ -164,29 +164,29 @@ system.cpu.l2cache.blocked_cycles_no_mshrs 0 # system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.demand_accesses 456190 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 2564.564334 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 1563.181738 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_miss_latency 13000 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 11000 # average overall mshr miss latency system.cpu.l2cache.demand_hits 430092 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 66930000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency 339274000 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_rate 0.057209 # miss rate for demand accesses system.cpu.l2cache.demand_misses 26098 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 40795917 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 287078000 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_rate 0.057209 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_misses 26098 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.overall_accesses 781913 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 2564.564334 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 1563.181738 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_miss_latency 13000 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 11000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.cpu.l2cache.overall_hits 755815 # number of overall hits -system.cpu.l2cache.overall_miss_latency 66930000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency 339274000 # number of overall miss cycles system.cpu.l2cache.overall_miss_rate 0.033377 # miss rate for overall accesses system.cpu.l2cache.overall_misses 26098 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 40795917 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 287078000 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_rate 0.033377 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_misses 26098 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -203,12 +203,12 @@ system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.l2cache.replacements 903 # number of replacements system.cpu.l2cache.sampled_refs 26098 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 24878.910085 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 24875.090462 # Cycle average of tags in use system.cpu.l2cache.total_refs 755815 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 883 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 378869140000 # number of cpu cycles simulated +system.cpu.numCycles 760892614000 # number of cpu cycles simulated system.cpu.num_insts 601856965 # Number of instructions executed system.cpu.num_refs 154862034 # Number of memory references system.cpu.workload.PROG:num_syscalls 17 # Number of system calls |