diff options
| author | Nathan Binkert <nate@binkert.org> | 2011-04-19 18:45:23 -0700 |
|---|---|---|
| committer | Nathan Binkert <nate@binkert.org> | 2011-04-19 18:45:23 -0700 |
| commit | 8c1563096c5aaf4123bf9ce5116aff3ce44dfd3b (patch) | |
| tree | 8caf62f25cfd5047cd4f2c0f357267be9d79d7c4 /tests/long/00.gzip/ref/alpha/tru64 | |
| parent | 63371c86648ed65a453a95aec80f326f15a9666d (diff) | |
| download | gem5-8c1563096c5aaf4123bf9ce5116aff3ce44dfd3b.tar.xz | |
tests: update stats for name changes
Diffstat (limited to 'tests/long/00.gzip/ref/alpha/tru64')
11 files changed, 249 insertions, 244 deletions
diff --git a/tests/long/00.gzip/ref/alpha/tru64/inorder-timing/config.ini b/tests/long/00.gzip/ref/alpha/tru64/inorder-timing/config.ini index 85d434144..23a53cd4f 100644 --- a/tests/long/00.gzip/ref/alpha/tru64/inorder-timing/config.ini +++ b/tests/long/00.gzip/ref/alpha/tru64/inorder-timing/config.ini @@ -86,6 +86,7 @@ assoc=2 block_size=64 forward_snoops=true hash_delay=1 +is_top_level=true latency=1000 max_miss_count=0 mshrs=10 @@ -121,6 +122,7 @@ assoc=2 block_size=64 forward_snoops=true hash_delay=1 +is_top_level=true latency=1000 max_miss_count=0 mshrs=10 @@ -156,6 +158,7 @@ assoc=2 block_size=64 forward_snoops=true hash_delay=1 +is_top_level=false latency=10000 max_miss_count=0 mshrs=10 diff --git a/tests/long/00.gzip/ref/alpha/tru64/inorder-timing/simout b/tests/long/00.gzip/ref/alpha/tru64/inorder-timing/simout index 8f9b1263d..ff066f3a4 100755 --- a/tests/long/00.gzip/ref/alpha/tru64/inorder-timing/simout +++ b/tests/long/00.gzip/ref/alpha/tru64/inorder-timing/simout @@ -5,10 +5,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Feb 23 2011 05:47:47 -M5 revision Unknown -M5 started Feb 23 2011 05:49:05 -M5 executing on m55-001.pool +M5 compiled Apr 19 2011 11:52:53 +M5 started Apr 19 2011 11:58:24 +M5 executing on maize command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/inorder-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/inorder-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/00.gzip/ref/alpha/tru64/inorder-timing/stats.txt b/tests/long/00.gzip/ref/alpha/tru64/inorder-timing/stats.txt index 97f36d33a..74577bc37 100644 --- a/tests/long/00.gzip/ref/alpha/tru64/inorder-timing/stats.txt +++ b/tests/long/00.gzip/ref/alpha/tru64/inorder-timing/stats.txt @@ -1,37 +1,25 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 145740 # Simulator instruction rate (inst/s) -host_mem_usage 390376 # Number of bytes of host memory used -host_seconds 4129.65 # Real time elapsed on the host -host_tick_rate 63356930 # Simulator tick rate (ticks/s) +host_inst_rate 209357 # Simulator instruction rate (inst/s) +host_mem_usage 403360 # Number of bytes of host memory used +host_seconds 2874.78 # Real time elapsed on the host +host_tick_rate 91012809 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 601856964 # Number of instructions simulated sim_seconds 0.261642 # Number of seconds simulated sim_ticks 261641972500 # Number of ticks simulated -system.cpu.AGEN-Unit.agens 155868116 # Number of Address Generations -system.cpu.Branch-Predictor.BTBHitPct 90.344266 # BTB Hit Percentage -system.cpu.Branch-Predictor.BTBHits 29143677 # Number of BTB hits -system.cpu.Branch-Predictor.BTBLookups 32258469 # Number of BTB lookups -system.cpu.Branch-Predictor.RASInCorrect 6 # Number of incorrect RAS predictions. -system.cpu.Branch-Predictor.condIncorrect 22153653 # Number of conditional branches incorrect -system.cpu.Branch-Predictor.condPredicted 59309256 # Number of conditional branches predicted -system.cpu.Branch-Predictor.lookups 64114012 # Number of BP lookups -system.cpu.Branch-Predictor.predictedNotTaken 31921338 # Number of Branches Predicted As Not Taken (False). -system.cpu.Branch-Predictor.predictedTaken 32192674 # Number of Branches Predicted As Taken (True). -system.cpu.Branch-Predictor.usedRAS 1197609 # Number of times the RAS was used to get a target. -system.cpu.Execution-Unit.executions 419011350 # Number of Instructions Executed. -system.cpu.Execution-Unit.mispredictPct 35.419120 # Percentage of Incorrect Branches Predicts -system.cpu.Execution-Unit.mispredicted 22153653 # Number of Branches Incorrectly Predicted -system.cpu.Execution-Unit.predicted 40393506 # Number of Branches Incorrectly Predicted -system.cpu.Execution-Unit.predictedNotTakenIncorrect 19275234 # Number of Branches Incorrectly Predicted As Not Taken). -system.cpu.Execution-Unit.predictedTakenIncorrect 2878419 # Number of Branches Incorrectly Predicted As Taken. -system.cpu.Mult-Div-Unit.divides 0 # Number of Divide Operations Executed -system.cpu.Mult-Div-Unit.multiplies 6482 # Number of Multipy Operations Executed -system.cpu.RegFile-Manager.regFileAccesses 1022190210 # Number of Total Accesses (Read+Write) to the Register File -system.cpu.RegFile-Manager.regFileReads 558335321 # Number of Reads from Register File -system.cpu.RegFile-Manager.regFileWrites 463854889 # Number of Writes to Register File -system.cpu.RegFile-Manager.regForwards 256259728 # Number of Registers Read Through Forwarding Logic system.cpu.activity 88.058146 # Percentage of cycles cpu is active +system.cpu.agen_unit.agens 155868116 # Number of Address Generations +system.cpu.branch_predictor.BTBHitPct 90.344266 # BTB Hit Percentage +system.cpu.branch_predictor.BTBHits 29143677 # Number of BTB hits +system.cpu.branch_predictor.BTBLookups 32258469 # Number of BTB lookups +system.cpu.branch_predictor.RASInCorrect 6 # Number of incorrect RAS predictions. +system.cpu.branch_predictor.condIncorrect 22153653 # Number of conditional branches incorrect +system.cpu.branch_predictor.condPredicted 59309256 # Number of conditional branches predicted +system.cpu.branch_predictor.lookups 64114012 # Number of BP lookups +system.cpu.branch_predictor.predictedNotTaken 31921338 # Number of Branches Predicted As Not Taken (False). +system.cpu.branch_predictor.predictedTaken 32192674 # Number of Branches Predicted As Taken (True). +system.cpu.branch_predictor.usedRAS 1197609 # Number of times the RAS was used to get a target. system.cpu.comBranches 62547159 # Number of Branches instructions committed system.cpu.comFloats 24 # Number of Floating Point instructions committed system.cpu.comInts 349039879 # Number of Integer instructions committed @@ -88,8 +76,8 @@ system.cpu.dcache.demand_mshr_misses 455395 # nu system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.occ_%::0 0.998946 # Average percentage of cache occupancy system.cpu.dcache.occ_blocks::0 4091.682212 # Average occupied blocks per context +system.cpu.dcache.occ_percent::0 0.998946 # Average percentage of cache occupancy system.cpu.dcache.overall_accesses 153965363 # number of overall (read+write) accesses system.cpu.dcache.overall_avg_miss_latency 21854.685324 # average overall miss latency system.cpu.dcache.overall_avg_mshr_miss_latency 19449.234181 # average overall mshr miss latency @@ -127,6 +115,12 @@ system.cpu.dtb.write_accesses 39453623 # DT system.cpu.dtb.write_acv 0 # DTB write access violations system.cpu.dtb.write_hits 39451321 # DTB write hits system.cpu.dtb.write_misses 2302 # DTB write misses +system.cpu.execution_unit.executions 419011350 # Number of Instructions Executed. +system.cpu.execution_unit.mispredictPct 35.419120 # Percentage of Incorrect Branches Predicts +system.cpu.execution_unit.mispredicted 22153653 # Number of Branches Incorrectly Predicted +system.cpu.execution_unit.predicted 40393506 # Number of Branches Incorrectly Predicted +system.cpu.execution_unit.predictedNotTakenIncorrect 19275234 # Number of Branches Incorrectly Predicted As Not Taken). +system.cpu.execution_unit.predictedTakenIncorrect 2878419 # Number of Branches Incorrectly Predicted As Taken. system.cpu.icache.ReadReq_accesses 25645163 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_avg_miss_latency 55761.178862 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_mshr_miss_latency 53508.177570 # average ReadReq mshr miss latency @@ -160,8 +154,8 @@ system.cpu.icache.demand_mshr_misses 856 # nu system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.occ_%::0 0.355592 # Average percentage of cache occupancy system.cpu.icache.occ_blocks::0 728.253324 # Average occupied blocks per context +system.cpu.icache.occ_percent::0 0.355592 # Average percentage of cache occupancy system.cpu.icache.overall_accesses 25645163 # number of overall (read+write) accesses system.cpu.icache.overall_avg_miss_latency 55761.178862 # average overall miss latency system.cpu.icache.overall_avg_mshr_miss_latency 53508.177570 # average overall mshr miss latency @@ -246,10 +240,10 @@ system.cpu.l2cache.demand_mshr_misses 92098 # nu system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.occ_%::0 0.050363 # Average percentage of cache occupancy -system.cpu.l2cache.occ_%::1 0.487947 # Average percentage of cache occupancy system.cpu.l2cache.occ_blocks::0 1650.286010 # Average occupied blocks per context system.cpu.l2cache.occ_blocks::1 15989.036396 # Average occupied blocks per context +system.cpu.l2cache.occ_percent::0 0.050363 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::1 0.487947 # Average percentage of cache occupancy system.cpu.l2cache.overall_accesses 456251 # number of overall (read+write) accesses system.cpu.l2cache.overall_avg_miss_latency 52157.973029 # average overall miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 40004.212904 # average overall mshr miss latency @@ -271,31 +265,37 @@ system.cpu.l2cache.tagsinuse 17639.322406 # Cy system.cpu.l2cache.total_refs 445702 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 59346 # number of writebacks +system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed +system.cpu.mult_div_unit.multiplies 6482 # Number of Multipy Operations Executed system.cpu.numCycles 523283946 # number of cpu cycles simulated system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.regfile_manager.regFileAccesses 1022190210 # Number of Total Accesses (Read+Write) to the Register File +system.cpu.regfile_manager.regFileReads 558335321 # Number of Reads from Register File +system.cpu.regfile_manager.regFileWrites 463854889 # Number of Writes to Register File +system.cpu.regfile_manager.regForwards 256259728 # Number of Registers Read Through Forwarding Logic system.cpu.runCycles 460794140 # Number of cycles cpu stages are processed. system.cpu.smtCommittedInsts 0 # Number of SMT Instructions Simulated (Per-Thread) system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode system.cpu.smt_cpi no_value # CPI: Total SMT-CPI system.cpu.smt_ipc no_value # IPC: Total SMT-IPC -system.cpu.stage-0.idleCycles 186436323 # Number of cycles 0 instructions are processed. -system.cpu.stage-0.runCycles 336847623 # Number of cycles 1+ instructions are processed. -system.cpu.stage-0.utilization 64.371863 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage-1.idleCycles 209154116 # Number of cycles 0 instructions are processed. -system.cpu.stage-1.runCycles 314129830 # Number of cycles 1+ instructions are processed. -system.cpu.stage-1.utilization 60.030473 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage-2.idleCycles 197582511 # Number of cycles 0 instructions are processed. -system.cpu.stage-2.runCycles 325701435 # Number of cycles 1+ instructions are processed. -system.cpu.stage-2.utilization 62.241817 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage-3.idleCycles 410314498 # Number of cycles 0 instructions are processed. -system.cpu.stage-3.runCycles 112969448 # Number of cycles 1+ instructions are processed. -system.cpu.stage-3.utilization 21.588556 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage-4.idleCycles 180086100 # Number of cycles 0 instructions are processed. -system.cpu.stage-4.runCycles 343197846 # Number of cycles 1+ instructions are processed. -system.cpu.stage-4.utilization 65.585396 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage0.idleCycles 186436323 # Number of cycles 0 instructions are processed. +system.cpu.stage0.runCycles 336847623 # Number of cycles 1+ instructions are processed. +system.cpu.stage0.utilization 64.371863 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage1.idleCycles 209154116 # Number of cycles 0 instructions are processed. +system.cpu.stage1.runCycles 314129830 # Number of cycles 1+ instructions are processed. +system.cpu.stage1.utilization 60.030473 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage2.idleCycles 197582511 # Number of cycles 0 instructions are processed. +system.cpu.stage2.runCycles 325701435 # Number of cycles 1+ instructions are processed. +system.cpu.stage2.utilization 62.241817 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage3.idleCycles 410314498 # Number of cycles 0 instructions are processed. +system.cpu.stage3.runCycles 112969448 # Number of cycles 1+ instructions are processed. +system.cpu.stage3.utilization 21.588556 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage4.idleCycles 180086100 # Number of cycles 0 instructions are processed. +system.cpu.stage4.runCycles 343197846 # Number of cycles 1+ instructions are processed. +system.cpu.stage4.utilization 65.585396 # Percentage of cycles stage was utilized (processing insts). system.cpu.threadCycles 508404874 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) system.cpu.timesIdled 455729 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.workload.PROG:num_syscalls 17 # Number of system calls +system.cpu.workload.num_syscalls 17 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/config.ini b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/config.ini index 8d44452f2..2c97093b4 100644 --- a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/config.ini +++ b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/config.ini @@ -25,6 +25,8 @@ BTBEntries=4096 BTBTagSize=16 LFSTSize=1024 LQEntries=32 +LSQCheckLoads=true +LSQDepCheckShift=4 RASSize=16 SQEntries=32 SSITSize=1024 diff --git a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/simout b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/simout index 6c138b362..10e34acb3 100755 --- a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/simout +++ b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/simout @@ -5,9 +5,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Mar 17 2011 21:44:37 -M5 started Mar 17 2011 22:44:08 -M5 executing on zizzer +M5 compiled Apr 19 2011 11:52:53 +M5 started Apr 19 2011 12:05:54 +M5 executing on maize command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/stats.txt index 93acfbb63..bb82434d0 100644 --- a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 243015 # Simulator instruction rate (inst/s) -host_mem_usage 208616 # Number of bytes of host memory used -host_seconds 2327.23 # Real time elapsed on the host -host_tick_rate 69757618 # Simulator tick rate (ticks/s) +host_inst_rate 385051 # Simulator instruction rate (inst/s) +host_mem_usage 204468 # Number of bytes of host memory used +host_seconds 1468.77 # Real time elapsed on the host +host_tick_rate 110529153 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 565552443 # Number of instructions simulated sim_seconds 0.162342 # Number of seconds simulated @@ -16,38 +16,38 @@ system.cpu.BPredUnit.condIncorrect 4119052 # Nu system.cpu.BPredUnit.condPredicted 70244988 # Number of conditional branches predicted system.cpu.BPredUnit.lookups 76158972 # Number of BP lookups system.cpu.BPredUnit.usedRAS 1672188 # Number of times the RAS was used to get a target. -system.cpu.commit.COM:branches 62547159 # Number of branches committed -system.cpu.commit.COM:bw_lim_events 20370282 # number cycles where commit BW limit reached -system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits -system.cpu.commit.COM:committed_per_cycle::samples 315015358 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::mean 1.910564 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::stdev 2.344745 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::0 102187516 32.44% 32.44% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::1 100337503 31.85% 64.29% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::2 36333939 11.53% 75.82% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::3 9834278 3.12% 78.95% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::4 9585018 3.04% 81.99% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::5 21675104 6.88% 88.87% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::6 13171126 4.18% 93.05% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::7 1520592 0.48% 93.53% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::8 20370282 6.47% 100.00% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::total 315015358 # Number of insts commited each cycle -system.cpu.commit.COM:count 601856963 # Number of instructions committed -system.cpu.commit.COM:fp_insts 1520 # Number of committed floating point instructions. -system.cpu.commit.COM:function_calls 1197610 # Number of function calls committed. -system.cpu.commit.COM:int_insts 563954763 # Number of committed integer instructions. -system.cpu.commit.COM:loads 114514042 # Number of loads committed -system.cpu.commit.COM:membars 0 # Number of memory barriers committed -system.cpu.commit.COM:refs 153965363 # Number of memory references committed -system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed system.cpu.commit.branchMispredicts 4118243 # The number of times a branch was mispredicted +system.cpu.commit.branches 62547159 # Number of branches committed +system.cpu.commit.bw_lim_events 20370282 # number cycles where commit BW limit reached +system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits system.cpu.commit.commitCommittedInsts 601856963 # The number of committed instructions system.cpu.commit.commitNonSpecStalls 17 # The number of times commit has been forced to stall to communicate backwards system.cpu.commit.commitSquashedInsts 59876142 # The number of squashed insts skipped by commit +system.cpu.commit.committed_per_cycle::samples 315015358 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.910564 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.344745 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 102187516 32.44% 32.44% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 100337503 31.85% 64.29% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 36333939 11.53% 75.82% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 9834278 3.12% 78.95% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 9585018 3.04% 81.99% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 21675104 6.88% 88.87% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 13171126 4.18% 93.05% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 1520592 0.48% 93.53% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 20370282 6.47% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 315015358 # Number of insts commited each cycle +system.cpu.commit.count 601856963 # Number of instructions committed +system.cpu.commit.fp_insts 1520 # Number of committed floating point instructions. +system.cpu.commit.function_calls 1197610 # Number of function calls committed. +system.cpu.commit.int_insts 563954763 # Number of committed integer instructions. +system.cpu.commit.loads 114514042 # Number of loads committed +system.cpu.commit.membars 0 # Number of memory barriers committed +system.cpu.commit.refs 153965363 # Number of memory references committed +system.cpu.commit.swp_count 0 # Number of s/w prefetches committed system.cpu.committedInsts 565552443 # Number of Instructions Simulated system.cpu.committedInsts_total 565552443 # Number of Instructions Simulated system.cpu.cpi 0.574101 # CPI: Cycles Per Instruction @@ -98,8 +98,8 @@ system.cpu.dcache.demand_mshr_misses 475134 # nu system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.occ_%::0 0.999549 # Average percentage of cache occupancy system.cpu.dcache.occ_blocks::0 4094.151824 # Average occupied blocks per context +system.cpu.dcache.occ_percent::0 0.999549 # Average percentage of cache occupancy system.cpu.dcache.overall_accesses 151655852 # number of overall (read+write) accesses system.cpu.dcache.overall_avg_miss_latency 14624.181040 # average overall miss latency system.cpu.dcache.overall_avg_mshr_miss_latency 9493.104038 # average overall mshr miss latency @@ -121,15 +121,15 @@ system.cpu.dcache.tagsinuse 4094.151824 # Cy system.cpu.dcache.total_refs 149582206 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 126677000 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 423176 # number of writebacks -system.cpu.decode.DECODE:BlockedCycles 44833716 # Number of cycles decode is blocked -system.cpu.decode.DECODE:BranchMispred 844 # Number of times decode detected a branch misprediction -system.cpu.decode.DECODE:BranchResolved 4163323 # Number of times decode resolved a branch -system.cpu.decode.DECODE:DecodedInsts 687863087 # Number of instructions handled by decode -system.cpu.decode.DECODE:IdleCycles 142213399 # Number of cycles decode is idle -system.cpu.decode.DECODE:RunCycles 122593858 # Number of cycles decode is running -system.cpu.decode.DECODE:SquashCycles 9601978 # Number of cycles decode is squashing -system.cpu.decode.DECODE:SquashedInsts 3402 # Number of squashed instructions handled by decode -system.cpu.decode.DECODE:UnblockCycles 5374385 # Number of cycles decode is unblocking +system.cpu.decode.BlockedCycles 44833716 # Number of cycles decode is blocked +system.cpu.decode.BranchMispred 844 # Number of times decode detected a branch misprediction +system.cpu.decode.BranchResolved 4163323 # Number of times decode resolved a branch +system.cpu.decode.DecodedInsts 687863087 # Number of instructions handled by decode +system.cpu.decode.IdleCycles 142213399 # Number of cycles decode is idle +system.cpu.decode.RunCycles 122593858 # Number of cycles decode is running +system.cpu.decode.SquashCycles 9601978 # Number of cycles decode is squashing +system.cpu.decode.SquashedInsts 3402 # Number of squashed instructions handled by decode +system.cpu.decode.UnblockCycles 5374385 # Number of cycles decode is unblocking system.cpu.dtb.data_accesses 163150258 # DTB accesses system.cpu.dtb.data_acv 0 # DTB access violations system.cpu.dtb.data_hits 163097305 # DTB hits @@ -209,8 +209,8 @@ system.cpu.icache.demand_mshr_misses 909 # nu system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.occ_%::0 0.378270 # Average percentage of cache occupancy system.cpu.icache.occ_blocks::0 774.695980 # Average occupied blocks per context +system.cpu.icache.occ_percent::0 0.378270 # Average percentage of cache occupancy system.cpu.icache.overall_accesses 65447834 # number of overall (read+write) accesses system.cpu.icache.overall_avg_miss_latency 36501.303215 # average overall miss latency system.cpu.icache.overall_avg_mshr_miss_latency 35511.551155 # average overall mshr miss latency @@ -233,21 +233,13 @@ system.cpu.icache.total_refs 65446683 # To system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks system.cpu.idleCycles 67100 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.iew.EXEC:branches 67449018 # Number of branches executed -system.cpu.iew.EXEC:nop 43212719 # number of nop insts executed -system.cpu.iew.EXEC:rate 1.845435 # Inst execution rate -system.cpu.iew.EXEC:refs 163178153 # number of memory reference insts executed -system.cpu.iew.EXEC:stores 40932468 # Number of stores executed -system.cpu.iew.EXEC:swp 0 # number of swp insts executed -system.cpu.iew.WB:consumers 486897348 # num instructions consuming a value -system.cpu.iew.WB:count 595948678 # cumulative count of insts written-back -system.cpu.iew.WB:fanout 0.812979 # average fanout of values written-back -system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.WB:producers 395837342 # num instructions producing a value -system.cpu.iew.WB:rate 1.835470 # insts written-back per cycle -system.cpu.iew.WB:sent 597097102 # cumulative count of insts sent to commit system.cpu.iew.branchMispredicts 4605504 # Number of branch mispredicts detected at execute +system.cpu.iew.exec_branches 67449018 # Number of branches executed +system.cpu.iew.exec_nop 43212719 # number of nop insts executed +system.cpu.iew.exec_rate 1.845435 # Inst execution rate +system.cpu.iew.exec_refs 163178153 # number of memory reference insts executed +system.cpu.iew.exec_stores 40932468 # Number of stores executed +system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.iewBlockCycles 1354512 # Number of cycles IEW is blocking system.cpu.iew.iewDispLoadInsts 125962189 # Number of dispatched load instructions system.cpu.iew.iewDispNonSpecInsts 25 # Number of dispatched non-speculative instructions @@ -275,103 +267,93 @@ system.cpu.iew.lsq.thread.0.squashedStores 3134413 # system.cpu.iew.memOrderViolationEvents 24101 # Number of memory order violations system.cpu.iew.predictedNotTakenIncorrect 952315 # Number of branches that were predicted not taken incorrectly system.cpu.iew.predictedTakenIncorrect 3653189 # Number of branches that were predicted taken incorrectly +system.cpu.iew.wb_consumers 486897348 # num instructions consuming a value +system.cpu.iew.wb_count 595948678 # cumulative count of insts written-back +system.cpu.iew.wb_fanout 0.812979 # average fanout of values written-back +system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ +system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ +system.cpu.iew.wb_producers 395837342 # num instructions producing a value +system.cpu.iew.wb_rate 1.835470 # insts written-back per cycle +system.cpu.iew.wb_sent 597097102 # cumulative count of insts sent to commit system.cpu.int_regfile_reads 844972523 # number of integer regfile reads system.cpu.int_regfile_writes 489243634 # number of integer regfile writes system.cpu.ipc 1.741853 # IPC: Instructions Per Cycle system.cpu.ipc_total 1.741853 # IPC: Total IPC of All Threads -system.cpu.iq.ISSUE:FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntAlu 439577743 72.58% 72.58% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntMult 6656 0.00% 72.59% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 72.59% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatAdd 30 0.00% 72.59% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatCmp 5 0.00% 72.59% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatCvt 5 0.00% 72.59% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatMult 4 0.00% 72.59% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 72.59% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 72.59% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdAdd 0 0.00% 72.59% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdAddAcc 0 0.00% 72.59% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdAlu 0 0.00% 72.59% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdCmp 0 0.00% 72.59% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdCvt 0 0.00% 72.59% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdMisc 0 0.00% 72.59% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdMult 0 0.00% 72.59% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdMultAcc 0 0.00% 72.59% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdShift 0 0.00% 72.59% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdShiftAcc 0 0.00% 72.59% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdSqrt 0 0.00% 72.59% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatAdd 0 0.00% 72.59% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatAlu 0 0.00% 72.59% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatCmp 0 0.00% 72.59% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatCvt 0 0.00% 72.59% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatDiv 0 0.00% 72.59% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatMisc 0 0.00% 72.59% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatMult 0 0.00% 72.59% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatMultAcc 0 0.00% 72.59% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatSqrt 0 0.00% 72.59% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::MemRead 124281005 20.52% 93.11% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::MemWrite 41743673 6.89% 100.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::total 605609121 # Type of FU issued -system.cpu.iq.ISSUE:fu_busy_cnt 5929666 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_rate 0.009791 # FU busy rate (busy events/executed inst) -system.cpu.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntAlu 5228922 88.18% 88.18% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntMult 48 0.00% 88.18% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 88.18% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 88.18% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 88.18% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 88.18% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 88.18% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 88.18% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 88.18% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdAdd 0 0.00% 88.18% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdAddAcc 0 0.00% 88.18% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdAlu 0 0.00% 88.18% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdCmp 0 0.00% 88.18% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdCvt 0 0.00% 88.18% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdMisc 0 0.00% 88.18% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdMult 0 0.00% 88.18% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdMultAcc 0 0.00% 88.18% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdShift 0 0.00% 88.18% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdShiftAcc 0 0.00% 88.18% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdSqrt 0 0.00% 88.18% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatAdd 0 0.00% 88.18% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatAlu 0 0.00% 88.18% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatCmp 0 0.00% 88.18% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatCvt 0 0.00% 88.18% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatDiv 0 0.00% 88.18% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatMisc 0 0.00% 88.18% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatMult 0 0.00% 88.18% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatMultAcc 0 0.00% 88.18% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatSqrt 0 0.00% 88.18% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::MemRead 403247 6.80% 94.98% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::MemWrite 297449 5.02% 100.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:issued_per_cycle::samples 324617336 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::mean 1.865609 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.727719 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::0 90473429 27.87% 27.87% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::1 62743019 19.33% 47.20% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::2 78570143 24.20% 71.40% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::3 32526937 10.02% 81.42% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::4 31455135 9.69% 91.11% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::5 13029774 4.01% 95.13% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::6 14124566 4.35% 99.48% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::7 1126465 0.35% 99.83% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::8 567868 0.17% 100.00% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::total 324617336 # Number of insts issued each cycle -system.cpu.iq.ISSUE:rate 1.865224 # Inst issue rate +system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 439577743 72.58% 72.58% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 6656 0.00% 72.59% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 72.59% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 30 0.00% 72.59% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 5 0.00% 72.59% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 5 0.00% 72.59% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 4 0.00% 72.59% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 72.59% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 72.59% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 72.59% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 72.59% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 72.59% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 72.59% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 72.59% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 72.59% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 72.59% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 72.59% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 72.59% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 72.59% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 72.59% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 72.59% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 72.59% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 72.59% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 72.59% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 72.59% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 72.59% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 72.59% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 72.59% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 72.59% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 124281005 20.52% 93.11% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 41743673 6.89% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::total 605609121 # Type of FU issued system.cpu.iq.fp_alu_accesses 1669 # Number of floating point alu accesses system.cpu.iq.fp_inst_queue_reads 3317 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_wakeup_accesses 1594 # Number of floating instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_writes 1802 # Number of floating instruction queue writes +system.cpu.iq.fu_busy_cnt 5929666 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.009791 # FU busy rate (busy events/executed inst) +system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 5228922 88.18% 88.18% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 48 0.00% 88.18% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 88.18% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 88.18% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 88.18% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 88.18% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 88.18% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 88.18% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 88.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 88.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 88.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 88.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 88.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 88.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 88.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 88.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 88.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 88.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 88.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 88.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 88.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 88.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 88.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 88.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 88.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 88.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 88.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 88.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 88.18% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 403247 6.80% 94.98% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 297449 5.02% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.int_alu_accesses 611537118 # Number of integer alu accesses system.cpu.iq.int_inst_queue_reads 1541773318 # Number of integer instruction queue reads system.cpu.iq.int_inst_queue_wakeup_accesses 595947084 # Number of integer instruction queue wakeup accesses @@ -383,6 +365,24 @@ system.cpu.iq.iqSquashedInstsExamined 51673321 # Nu system.cpu.iq.iqSquashedInstsIssued 11391 # Number of squashed instructions issued system.cpu.iq.iqSquashedNonSpecRemoved 8 # Number of squashed non-spec instructions that were removed system.cpu.iq.iqSquashedOperandsExamined 26894119 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.issued_per_cycle::samples 324617336 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.865609 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.727719 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 90473429 27.87% 27.87% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 62743019 19.33% 47.20% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 78570143 24.20% 71.40% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 32526937 10.02% 81.42% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 31455135 9.69% 91.11% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 13029774 4.01% 95.13% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 14124566 4.35% 99.48% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 1126465 0.35% 99.83% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 567868 0.17% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 324617336 # Number of insts issued each cycle +system.cpu.iq.rate 1.865224 # Inst issue rate system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_hits 0 # DTB hits @@ -443,10 +443,10 @@ system.cpu.l2cache.demand_mshr_misses 92757 # nu system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.occ_%::0 0.052925 # Average percentage of cache occupancy -system.cpu.l2cache.occ_%::1 0.487884 # Average percentage of cache occupancy system.cpu.l2cache.occ_blocks::0 1734.245593 # Average occupied blocks per context system.cpu.l2cache.occ_blocks::1 15986.969370 # Average occupied blocks per context +system.cpu.l2cache.occ_percent::0 0.052925 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::1 0.487884 # Average percentage of cache occupancy system.cpu.l2cache.overall_accesses 476043 # number of overall (read+write) accesses system.cpu.l2cache.overall_avg_miss_latency 34447.863773 # average overall miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 31236.300225 # average overall mshr miss latency @@ -477,28 +477,28 @@ system.cpu.misc_regfile_writes 1 # nu system.cpu.numCycles 324684436 # number of cpu cycles simulated system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.rename.RENAME:BlockCycles 12564419 # Number of cycles rename is blocking -system.cpu.rename.RENAME:CommittedMaps 463854889 # Number of HB maps that are committed -system.cpu.rename.RENAME:IQFullEvents 31522766 # Number of times rename has blocked due to IQ full -system.cpu.rename.RENAME:IdleCycles 149604933 # Number of cycles rename is idle -system.cpu.rename.RENAME:LSQFullEvents 659383 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RENAME:ROBFullEvents 101 # Number of times rename has blocked due to ROB full -system.cpu.rename.RENAME:RenameLookups 894089158 # Number of register rename lookups that rename has made -system.cpu.rename.RENAME:RenamedInsts 678776451 # Number of instructions processed by rename -system.cpu.rename.RENAME:RenamedOperands 517767610 # Number of destination operands rename has renamed -system.cpu.rename.RENAME:RunCycles 115293181 # Number of cycles rename is running -system.cpu.rename.RENAME:SquashCycles 9601978 # Number of cycles rename is squashing -system.cpu.rename.RENAME:UnblockCycles 37552130 # Number of cycles rename is unblocking -system.cpu.rename.RENAME:UndoneMaps 53912721 # Number of HB maps that are undone due to squashing -system.cpu.rename.RENAME:fp_rename_lookups 1965 # Number of floating rename lookups -system.cpu.rename.RENAME:int_rename_lookups 894087193 # Number of integer rename lookups -system.cpu.rename.RENAME:serializeStallCycles 695 # count of cycles rename stalled for serializing inst -system.cpu.rename.RENAME:serializingInsts 31 # count of serializing insts renamed -system.cpu.rename.RENAME:skidInsts 73444449 # count of insts added to the skid buffer -system.cpu.rename.RENAME:tempSerializingInsts 30 # count of temporary serializing insts renamed +system.cpu.rename.BlockCycles 12564419 # Number of cycles rename is blocking +system.cpu.rename.CommittedMaps 463854889 # Number of HB maps that are committed +system.cpu.rename.IQFullEvents 31522766 # Number of times rename has blocked due to IQ full +system.cpu.rename.IdleCycles 149604933 # Number of cycles rename is idle +system.cpu.rename.LSQFullEvents 659383 # Number of times rename has blocked due to LSQ full +system.cpu.rename.ROBFullEvents 101 # Number of times rename has blocked due to ROB full +system.cpu.rename.RenameLookups 894089158 # Number of register rename lookups that rename has made +system.cpu.rename.RenamedInsts 678776451 # Number of instructions processed by rename +system.cpu.rename.RenamedOperands 517767610 # Number of destination operands rename has renamed +system.cpu.rename.RunCycles 115293181 # Number of cycles rename is running +system.cpu.rename.SquashCycles 9601978 # Number of cycles rename is squashing +system.cpu.rename.UnblockCycles 37552130 # Number of cycles rename is unblocking +system.cpu.rename.UndoneMaps 53912721 # Number of HB maps that are undone due to squashing +system.cpu.rename.fp_rename_lookups 1965 # Number of floating rename lookups +system.cpu.rename.int_rename_lookups 894087193 # Number of integer rename lookups +system.cpu.rename.serializeStallCycles 695 # count of cycles rename stalled for serializing inst +system.cpu.rename.serializingInsts 31 # count of serializing insts renamed +system.cpu.rename.skidInsts 73444449 # count of insts added to the skid buffer +system.cpu.rename.tempSerializingInsts 30 # count of temporary serializing insts renamed system.cpu.rob.rob_reads 956313792 # The number of ROB reads system.cpu.rob.rob_writes 1333072216 # The number of ROB writes system.cpu.timesIdled 2037 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.workload.PROG:num_syscalls 17 # Number of system calls +system.cpu.workload.num_syscalls 17 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/simout b/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/simout index b96d561c3..87e51a8e2 100755 --- a/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/simout +++ b/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/simout @@ -5,10 +5,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Feb 7 2011 01:47:18 -M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip -M5 started Feb 7 2011 01:47:37 -M5 executing on burrito +M5 compiled Apr 19 2011 11:52:53 +M5 started Apr 19 2011 11:58:35 +M5 executing on maize command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/simple-atomic -re tests/run.py build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/stats.txt b/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/stats.txt index 4dfa82a45..fdb2e2919 100644 --- a/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/stats.txt +++ b/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1697811 # Simulator instruction rate (inst/s) -host_mem_usage 218112 # Number of bytes of host memory used -host_seconds 354.49 # Real time elapsed on the host -host_tick_rate 848911876 # Simulator tick rate (ticks/s) +host_inst_rate 6401056 # Simulator instruction rate (inst/s) +host_mem_usage 195828 # Number of bytes of host memory used +host_seconds 94.02 # Real time elapsed on the host +host_tick_rate 3200547989 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 601856964 # Number of instructions simulated sim_seconds 0.300931 # Number of seconds simulated @@ -61,6 +61,6 @@ system.cpu.num_int_register_writes 463854847 # nu system.cpu.num_load_insts 114516673 # Number of load instructions system.cpu.num_mem_refs 153970296 # number of memory refs system.cpu.num_store_insts 39453623 # Number of store instructions -system.cpu.workload.PROG:num_syscalls 17 # Number of system calls +system.cpu.workload.num_syscalls 17 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/00.gzip/ref/alpha/tru64/simple-timing/config.ini b/tests/long/00.gzip/ref/alpha/tru64/simple-timing/config.ini index 5dbdc6426..50ef6266f 100644 --- a/tests/long/00.gzip/ref/alpha/tru64/simple-timing/config.ini +++ b/tests/long/00.gzip/ref/alpha/tru64/simple-timing/config.ini @@ -51,6 +51,7 @@ assoc=2 block_size=64 forward_snoops=true hash_delay=1 +is_top_level=true latency=1000 max_miss_count=0 mshrs=10 @@ -86,6 +87,7 @@ assoc=2 block_size=64 forward_snoops=true hash_delay=1 +is_top_level=true latency=1000 max_miss_count=0 mshrs=10 @@ -121,6 +123,7 @@ assoc=2 block_size=64 forward_snoops=true hash_delay=1 +is_top_level=false latency=10000 max_miss_count=0 mshrs=10 diff --git a/tests/long/00.gzip/ref/alpha/tru64/simple-timing/simout b/tests/long/00.gzip/ref/alpha/tru64/simple-timing/simout index 5133de4f2..dc72f58cf 100755 --- a/tests/long/00.gzip/ref/alpha/tru64/simple-timing/simout +++ b/tests/long/00.gzip/ref/alpha/tru64/simple-timing/simout @@ -5,10 +5,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Feb 7 2011 01:47:18 -M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip -M5 started Feb 7 2011 01:47:36 -M5 executing on burrito +M5 compiled Apr 19 2011 11:52:53 +M5 started Apr 19 2011 11:58:24 +M5 executing on maize command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/simple-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/00.gzip/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/00.gzip/ref/alpha/tru64/simple-timing/stats.txt index 0f44a109b..f9d483c5d 100644 --- a/tests/long/00.gzip/ref/alpha/tru64/simple-timing/stats.txt +++ b/tests/long/00.gzip/ref/alpha/tru64/simple-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 591495 # Simulator instruction rate (inst/s) -host_mem_usage 225828 # Number of bytes of host memory used -host_seconds 1017.52 # Real time elapsed on the host -host_tick_rate 752441266 # Simulator tick rate (ticks/s) +host_inst_rate 2829112 # Simulator instruction rate (inst/s) +host_mem_usage 203572 # Number of bytes of host memory used +host_seconds 212.74 # Real time elapsed on the host +host_tick_rate 3598913072 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 601856964 # Number of instructions simulated sim_seconds 0.765623 # Number of seconds simulated @@ -50,8 +50,8 @@ system.cpu.dcache.demand_mshr_misses 455395 # nu system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.occ_%::0 0.999553 # Average percentage of cache occupancy system.cpu.dcache.occ_blocks::0 4094.170317 # Average occupied blocks per context +system.cpu.dcache.occ_percent::0 0.999553 # Average percentage of cache occupancy system.cpu.dcache.overall_accesses 153965363 # number of overall (read+write) accesses system.cpu.dcache.overall_avg_miss_latency 22414.479737 # average overall miss latency system.cpu.dcache.overall_avg_mshr_miss_latency 19414.479737 # average overall mshr miss latency @@ -121,8 +121,8 @@ system.cpu.icache.demand_mshr_misses 795 # nu system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.occ_%::0 0.328778 # Average percentage of cache occupancy system.cpu.icache.occ_blocks::0 673.337154 # Average occupied blocks per context +system.cpu.icache.occ_percent::0 0.328778 # Average percentage of cache occupancy system.cpu.icache.overall_accesses 601861898 # number of overall (read+write) accesses system.cpu.icache.overall_avg_miss_latency 56000 # average overall miss latency system.cpu.icache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency @@ -205,10 +205,10 @@ system.cpu.l2cache.demand_mshr_misses 92031 # nu system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.occ_%::0 0.052565 # Average percentage of cache occupancy -system.cpu.l2cache.occ_%::1 0.491366 # Average percentage of cache occupancy system.cpu.l2cache.occ_blocks::0 1722.436058 # Average occupied blocks per context system.cpu.l2cache.occ_blocks::1 16101.078831 # Average occupied blocks per context +system.cpu.l2cache.occ_percent::0 0.052565 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::1 0.491366 # Average percentage of cache occupancy system.cpu.l2cache.overall_accesses 456190 # number of overall (read+write) accesses system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency @@ -250,6 +250,6 @@ system.cpu.num_int_register_writes 463854847 # nu system.cpu.num_load_insts 114516673 # Number of load instructions system.cpu.num_mem_refs 153970296 # number of memory refs system.cpu.num_store_insts 39453623 # Number of store instructions -system.cpu.workload.PROG:num_syscalls 17 # Number of system calls +system.cpu.workload.num_syscalls 17 # Number of system calls ---------- End Simulation Statistics ---------- |