summaryrefslogtreecommitdiff
path: root/tests/long/00.gzip/ref/alpha/tru64
diff options
context:
space:
mode:
authorAli Saidi <Ali.Saidi@ARM.com>2011-01-18 16:30:06 -0600
committerAli Saidi <Ali.Saidi@ARM.com>2011-01-18 16:30:06 -0600
commit9b67f3723e48efdd0a0b640ff82cfcf8aad3a659 (patch)
tree79c5001cce6b9d92d1ad04d4a2cd4e442f56803c /tests/long/00.gzip/ref/alpha/tru64
parent77853b9f529947c3a9db78ef3458289f387289ce (diff)
downloadgem5-9b67f3723e48efdd0a0b640ff82cfcf8aad3a659.tar.xz
Stats: Update stats for previous set of patches.
Diffstat (limited to 'tests/long/00.gzip/ref/alpha/tru64')
-rwxr-xr-xtests/long/00.gzip/ref/alpha/tru64/o3-timing/simout6
-rw-r--r--tests/long/00.gzip/ref/alpha/tru64/o3-timing/stats.txt11
2 files changed, 9 insertions, 8 deletions
diff --git a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/simout b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/simout
index 57a3abb33..a359bdb55 100755
--- a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/simout
+++ b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/simout
@@ -5,9 +5,9 @@ The Regents of The University of Michigan
All Rights Reserved
-M5 compiled Nov 15 2010 08:52:32
-M5 revision f440cdaf1c2d+ 7743+ default tip
-M5 started Nov 15 2010 08:53:40
+M5 compiled Jan 17 2011 16:24:53
+M5 revision f72d94f8c275 7839 default qtip tip outgoing.patch qbase
+M5 started Jan 17 2011 16:40:29
M5 executing on zizzer
command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/o3-timing
Global frequency set at 1000000000000 ticks per second
diff --git a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/stats.txt
index 2bb965158..240486239 100644
--- a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/stats.txt
+++ b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/stats.txt
@@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ----------
-host_inst_rate 195051 # Simulator instruction rate (inst/s)
-host_mem_usage 206584 # Number of bytes of host memory used
-host_seconds 2899.51 # Real time elapsed on the host
-host_tick_rate 56140502 # Simulator tick rate (ticks/s)
+host_inst_rate 207877 # Simulator instruction rate (inst/s)
+host_mem_usage 206352 # Number of bytes of host memory used
+host_seconds 2720.61 # Real time elapsed on the host
+host_tick_rate 59832123 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 565552443 # Number of instructions simulated
sim_seconds 0.162780 # Number of seconds simulated
@@ -145,9 +145,10 @@ system.cpu.dtb.write_hits 40819876 # DT
system.cpu.dtb.write_misses 27547 # DTB write misses
system.cpu.fetch.Branches 76295210 # Number of branches that fetch encountered
system.cpu.fetch.CacheLines 65560315 # Number of cache lines fetched
-system.cpu.fetch.Cycles 195638983 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.Cycles 130078631 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.IcacheSquashes 1304986 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.Insts 697895611 # Number of instructions fetch has processed
+system.cpu.fetch.MiscStallCycles 37 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.SquashCycles 4169829 # Number of cycles fetch has spent squashing
system.cpu.fetch.branchRate 0.234351 # Number of branch fetches per cycle
system.cpu.fetch.icacheStallCycles 65560315 # Number of cycles fetch is stalled on an Icache miss