summaryrefslogtreecommitdiff
path: root/tests/long/00.gzip/ref/arm/linux
diff options
context:
space:
mode:
authorAli Saidi <Ali.Saidi@ARM.com>2011-01-18 16:30:06 -0600
committerAli Saidi <Ali.Saidi@ARM.com>2011-01-18 16:30:06 -0600
commitf7885b8f260ca11c2f4a405525d9fc4e554f41a8 (patch)
tree7843d9030dd422473d7efd5a4e2a0fd787e2b7f8 /tests/long/00.gzip/ref/arm/linux
parent9b67f3723e48efdd0a0b640ff82cfcf8aad3a659 (diff)
downloadgem5-f7885b8f260ca11c2f4a405525d9fc4e554f41a8.tar.xz
ARM/O3: Add regressions for ARM w/ O3 CPU.
Diffstat (limited to 'tests/long/00.gzip/ref/arm/linux')
-rw-r--r--tests/long/00.gzip/ref/arm/linux/o3-timing/config.ini517
-rwxr-xr-xtests/long/00.gzip/ref/arm/linux/o3-timing/simerr89
-rwxr-xr-xtests/long/00.gzip/ref/arm/linux/o3-timing/simout46
-rw-r--r--tests/long/00.gzip/ref/arm/linux/o3-timing/stats.txt494
4 files changed, 1146 insertions, 0 deletions
diff --git a/tests/long/00.gzip/ref/arm/linux/o3-timing/config.ini b/tests/long/00.gzip/ref/arm/linux/o3-timing/config.ini
new file mode 100644
index 000000000..1ca0fc2d1
--- /dev/null
+++ b/tests/long/00.gzip/ref/arm/linux/o3-timing/config.ini
@@ -0,0 +1,517 @@
+[root]
+type=Root
+children=system
+dummy=0
+
+[system]
+type=System
+children=cpu membus physmem
+mem_mode=atomic
+physmem=system.physmem
+
+[system.cpu]
+type=DerivO3CPU
+children=dcache dtb fuPool icache itb l2cache toL2Bus tracer workload
+BTBEntries=4096
+BTBTagSize=16
+LFSTSize=1024
+LQEntries=32
+RASSize=16
+SQEntries=32
+SSITSize=1024
+activity=0
+backComSize=5
+cachePorts=200
+checker=Null
+choiceCtrBits=2
+choicePredictorSize=8192
+clock=500
+commitToDecodeDelay=1
+commitToFetchDelay=1
+commitToIEWDelay=1
+commitToRenameDelay=1
+commitWidth=8
+cpu_id=0
+decodeToFetchDelay=1
+decodeToRenameDelay=1
+decodeWidth=8
+defer_registration=false
+dispatchWidth=8
+do_checkpoint_insts=true
+do_statistics_insts=true
+dtb=system.cpu.dtb
+fetchToDecodeDelay=1
+fetchTrapLatency=1
+fetchWidth=8
+forwardComSize=5
+fuPool=system.cpu.fuPool
+function_trace=false
+function_trace_start=0
+globalCtrBits=2
+globalHistoryBits=13
+globalPredictorSize=8192
+iewToCommitDelay=1
+iewToDecodeDelay=1
+iewToFetchDelay=1
+iewToRenameDelay=1
+instShiftAmt=2
+issueToExecuteDelay=1
+issueWidth=8
+itb=system.cpu.itb
+localCtrBits=2
+localHistoryBits=11
+localHistoryTableSize=2048
+localPredictorSize=2048
+max_insts_all_threads=0
+max_insts_any_thread=0
+max_loads_all_threads=0
+max_loads_any_thread=0
+numIQEntries=64
+numPhysFloatRegs=256
+numPhysIntRegs=256
+numROBEntries=192
+numRobs=1
+numThreads=1
+phase=0
+predType=tournament
+progress_interval=0
+renameToDecodeDelay=1
+renameToFetchDelay=1
+renameToIEWDelay=2
+renameToROBDelay=1
+renameWidth=8
+smtCommitPolicy=RoundRobin
+smtFetchPolicy=SingleThread
+smtIQPolicy=Partitioned
+smtIQThreshold=100
+smtLSQPolicy=Partitioned
+smtLSQThreshold=100
+smtNumFetchingThreads=1
+smtROBPolicy=Partitioned
+smtROBThreshold=100
+squashWidth=8
+system=system
+tracer=system.cpu.tracer
+trapLatency=13
+wbDepth=1
+wbWidth=8
+workload=system.cpu.workload
+dcache_port=system.cpu.dcache.cpu_side
+icache_port=system.cpu.icache.cpu_side
+
+[system.cpu.dcache]
+type=BaseCache
+addr_range=0:18446744073709551615
+assoc=2
+block_size=64
+forward_snoops=true
+hash_delay=1
+latency=1000
+max_miss_count=0
+mshrs=10
+num_cpus=1
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=10000
+prefetch_on_access=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+repl=Null
+size=262144
+subblock_size=0
+tgts_per_mshr=20
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.dcache_port
+mem_side=system.cpu.toL2Bus.port[1]
+
+[system.cpu.dtb]
+type=ArmTLB
+size=64
+
+[system.cpu.fuPool]
+type=FUPool
+children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8
+FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8
+
+[system.cpu.fuPool.FUList0]
+type=FUDesc
+children=opList
+count=6
+opList=system.cpu.fuPool.FUList0.opList
+
+[system.cpu.fuPool.FUList0.opList]
+type=OpDesc
+issueLat=1
+opClass=IntAlu
+opLat=1
+
+[system.cpu.fuPool.FUList1]
+type=FUDesc
+children=opList0 opList1
+count=2
+opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1
+
+[system.cpu.fuPool.FUList1.opList0]
+type=OpDesc
+issueLat=1
+opClass=IntMult
+opLat=3
+
+[system.cpu.fuPool.FUList1.opList1]
+type=OpDesc
+issueLat=19
+opClass=IntDiv
+opLat=20
+
+[system.cpu.fuPool.FUList2]
+type=FUDesc
+children=opList0 opList1 opList2
+count=4
+opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2
+
+[system.cpu.fuPool.FUList2.opList0]
+type=OpDesc
+issueLat=1
+opClass=FloatAdd
+opLat=2
+
+[system.cpu.fuPool.FUList2.opList1]
+type=OpDesc
+issueLat=1
+opClass=FloatCmp
+opLat=2
+
+[system.cpu.fuPool.FUList2.opList2]
+type=OpDesc
+issueLat=1
+opClass=FloatCvt
+opLat=2
+
+[system.cpu.fuPool.FUList3]
+type=FUDesc
+children=opList0 opList1 opList2
+count=2
+opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2
+
+[system.cpu.fuPool.FUList3.opList0]
+type=OpDesc
+issueLat=1
+opClass=FloatMult
+opLat=4
+
+[system.cpu.fuPool.FUList3.opList1]
+type=OpDesc
+issueLat=12
+opClass=FloatDiv
+opLat=12
+
+[system.cpu.fuPool.FUList3.opList2]
+type=OpDesc
+issueLat=24
+opClass=FloatSqrt
+opLat=24
+
+[system.cpu.fuPool.FUList4]
+type=FUDesc
+children=opList
+count=0
+opList=system.cpu.fuPool.FUList4.opList
+
+[system.cpu.fuPool.FUList4.opList]
+type=OpDesc
+issueLat=1
+opClass=MemRead
+opLat=1
+
+[system.cpu.fuPool.FUList5]
+type=FUDesc
+children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19
+count=4
+opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19
+
+[system.cpu.fuPool.FUList5.opList00]
+type=OpDesc
+issueLat=1
+opClass=SimdAdd
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList01]
+type=OpDesc
+issueLat=1
+opClass=SimdAddAcc
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList02]
+type=OpDesc
+issueLat=1
+opClass=SimdAlu
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList03]
+type=OpDesc
+issueLat=1
+opClass=SimdCmp
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList04]
+type=OpDesc
+issueLat=1
+opClass=SimdCvt
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList05]
+type=OpDesc
+issueLat=1
+opClass=SimdMisc
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList06]
+type=OpDesc
+issueLat=1
+opClass=SimdMult
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList07]
+type=OpDesc
+issueLat=1
+opClass=SimdMultAcc
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList08]
+type=OpDesc
+issueLat=1
+opClass=SimdShift
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList09]
+type=OpDesc
+issueLat=1
+opClass=SimdShiftAcc
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList10]
+type=OpDesc
+issueLat=1
+opClass=SimdSqrt
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList11]
+type=OpDesc
+issueLat=1
+opClass=SimdFloatAdd
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList12]
+type=OpDesc
+issueLat=1
+opClass=SimdFloatAlu
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList13]
+type=OpDesc
+issueLat=1
+opClass=SimdFloatCmp
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList14]
+type=OpDesc
+issueLat=1
+opClass=SimdFloatCvt
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList15]
+type=OpDesc
+issueLat=1
+opClass=SimdFloatDiv
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList16]
+type=OpDesc
+issueLat=1
+opClass=SimdFloatMisc
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList17]
+type=OpDesc
+issueLat=1
+opClass=SimdFloatMult
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList18]
+type=OpDesc
+issueLat=1
+opClass=SimdFloatMultAcc
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList19]
+type=OpDesc
+issueLat=1
+opClass=SimdFloatSqrt
+opLat=1
+
+[system.cpu.fuPool.FUList6]
+type=FUDesc
+children=opList
+count=0
+opList=system.cpu.fuPool.FUList6.opList
+
+[system.cpu.fuPool.FUList6.opList]
+type=OpDesc
+issueLat=1
+opClass=MemWrite
+opLat=1
+
+[system.cpu.fuPool.FUList7]
+type=FUDesc
+children=opList0 opList1
+count=4
+opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1
+
+[system.cpu.fuPool.FUList7.opList0]
+type=OpDesc
+issueLat=1
+opClass=MemRead
+opLat=1
+
+[system.cpu.fuPool.FUList7.opList1]
+type=OpDesc
+issueLat=1
+opClass=MemWrite
+opLat=1
+
+[system.cpu.fuPool.FUList8]
+type=FUDesc
+children=opList
+count=1
+opList=system.cpu.fuPool.FUList8.opList
+
+[system.cpu.fuPool.FUList8.opList]
+type=OpDesc
+issueLat=3
+opClass=IprAccess
+opLat=3
+
+[system.cpu.icache]
+type=BaseCache
+addr_range=0:18446744073709551615
+assoc=2
+block_size=64
+forward_snoops=true
+hash_delay=1
+latency=1000
+max_miss_count=0
+mshrs=10
+num_cpus=1
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=10000
+prefetch_on_access=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+repl=Null
+size=131072
+subblock_size=0
+tgts_per_mshr=20
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.icache_port
+mem_side=system.cpu.toL2Bus.port[0]
+
+[system.cpu.itb]
+type=ArmTLB
+size=64
+
+[system.cpu.l2cache]
+type=BaseCache
+addr_range=0:18446744073709551615
+assoc=2
+block_size=64
+forward_snoops=true
+hash_delay=1
+latency=1000
+max_miss_count=0
+mshrs=10
+num_cpus=1
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=10000
+prefetch_on_access=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+repl=Null
+size=2097152
+subblock_size=0
+tgts_per_mshr=5
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.toL2Bus.port[2]
+mem_side=system.membus.port[1]
+
+[system.cpu.toL2Bus]
+type=Bus
+block_size=64
+bus_id=0
+clock=1000
+header_cycles=1
+use_default_range=false
+width=64
+port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
+
+[system.cpu.tracer]
+type=ExeTracer
+
+[system.cpu.workload]
+type=LiveProcess
+cmd=gzip input.log 1
+cwd=build/ARM_SE/tests/fast/long/00.gzip/arm/linux/o3-timing
+egid=100
+env=
+errout=cerr
+euid=100
+executable=/chips/pd/randd/dist/cpu2000/binaries/arm/linux/gzip
+gid=100
+input=cin
+max_stack_size=67108864
+output=cout
+pid=100
+ppid=99
+simpoint=0
+system=system
+uid=100
+
+[system.membus]
+type=Bus
+block_size=64
+bus_id=0
+clock=1000
+header_cycles=1
+use_default_range=false
+width=64
+port=system.physmem.port[0] system.cpu.l2cache.mem_side
+
+[system.physmem]
+type=PhysicalMemory
+file=
+latency=30000
+latency_var=0
+null=false
+range=0:134217727
+zero=false
+port=system.membus.port[0]
+
diff --git a/tests/long/00.gzip/ref/arm/linux/o3-timing/simerr b/tests/long/00.gzip/ref/arm/linux/o3-timing/simerr
new file mode 100755
index 000000000..859694ad5
--- /dev/null
+++ b/tests/long/00.gzip/ref/arm/linux/o3-timing/simerr
@@ -0,0 +1,89 @@
+warn: Sockets disabled, not accepting gdb connections
+For more information see: http://www.m5sim.org/warn/d946bea6
+warn: Bad interworking branch address 0x7002.
+For more information see: http://www.m5sim.org/warn/55f199fd
+warn: Bad interworking branch address 0x7002.
+For more information see: http://www.m5sim.org/warn/55f199fd
+warn: Bad interworking branch address 0x7002.
+For more information see: http://www.m5sim.org/warn/55f199fd
+warn: Bad interworking branch address 0x7002.
+For more information see: http://www.m5sim.org/warn/55f199fd
+warn: Bad interworking branch address 0x7002.
+For more information see: http://www.m5sim.org/warn/55f199fd
+warn: Bad interworking branch address 0x7002.
+For more information see: http://www.m5sim.org/warn/55f199fd
+warn: Bad interworking branch address 0x7002.
+For more information see: http://www.m5sim.org/warn/55f199fd
+warn: Bad interworking branch address 0x7002.
+For more information see: http://www.m5sim.org/warn/55f199fd
+warn: Bad interworking branch address 0x7002.
+For more information see: http://www.m5sim.org/warn/55f199fd
+warn: Bad interworking branch address 0x7002.
+For more information see: http://www.m5sim.org/warn/55f199fd
+warn: Bad interworking branch address 0x7002.
+For more information see: http://www.m5sim.org/warn/55f199fd
+warn: Bad interworking branch address 0x7002.
+For more information see: http://www.m5sim.org/warn/55f199fd
+warn: Bad interworking branch address 0x7002.
+For more information see: http://www.m5sim.org/warn/55f199fd
+warn: Bad interworking branch address 0x7002.
+For more information see: http://www.m5sim.org/warn/55f199fd
+warn: Bad interworking branch address 0x7002.
+For more information see: http://www.m5sim.org/warn/55f199fd
+warn: Bad interworking branch address 0x7002.
+For more information see: http://www.m5sim.org/warn/55f199fd
+warn: Bad interworking branch address 0x7002.
+For more information see: http://www.m5sim.org/warn/55f199fd
+warn: Bad interworking branch address 0x7002.
+For more information see: http://www.m5sim.org/warn/55f199fd
+warn: Bad interworking branch address 0x7002.
+For more information see: http://www.m5sim.org/warn/55f199fd
+warn: Bad interworking branch address 0x7002.
+For more information see: http://www.m5sim.org/warn/55f199fd
+warn: Bad interworking branch address 0x7002.
+For more information see: http://www.m5sim.org/warn/55f199fd
+warn: Bad interworking branch address 0x7002.
+For more information see: http://www.m5sim.org/warn/55f199fd
+warn: Bad interworking branch address 0x7002.
+For more information see: http://www.m5sim.org/warn/55f199fd
+warn: Bad interworking branch address 0x7002.
+For more information see: http://www.m5sim.org/warn/55f199fd
+warn: Bad interworking branch address 0x7002.
+For more information see: http://www.m5sim.org/warn/55f199fd
+warn: Bad interworking branch address 0x7002.
+For more information see: http://www.m5sim.org/warn/55f199fd
+warn: Bad interworking branch address 0x7002.
+For more information see: http://www.m5sim.org/warn/55f199fd
+warn: Bad interworking branch address 0x7002.
+For more information see: http://www.m5sim.org/warn/55f199fd
+warn: Bad interworking branch address 0x7002.
+For more information see: http://www.m5sim.org/warn/55f199fd
+warn: Bad interworking branch address 0x7002.
+For more information see: http://www.m5sim.org/warn/55f199fd
+warn: Bad interworking branch address 0x7002.
+For more information see: http://www.m5sim.org/warn/55f199fd
+warn: Bad interworking branch address 0x7002.
+For more information see: http://www.m5sim.org/warn/55f199fd
+warn: Bad interworking branch address 0x7002.
+For more information see: http://www.m5sim.org/warn/55f199fd
+warn: Bad interworking branch address 0x7002.
+For more information see: http://www.m5sim.org/warn/55f199fd
+warn: Bad interworking branch address 0x7002.
+For more information see: http://www.m5sim.org/warn/55f199fd
+warn: Bad interworking branch address 0x7002.
+For more information see: http://www.m5sim.org/warn/55f199fd
+warn: Bad interworking branch address 0x7002.
+For more information see: http://www.m5sim.org/warn/55f199fd
+warn: Bad interworking branch address 0x7002.
+For more information see: http://www.m5sim.org/warn/55f199fd
+warn: Bad interworking branch address 0x7002.
+For more information see: http://www.m5sim.org/warn/55f199fd
+warn: Bad interworking branch address 0x7002.
+For more information see: http://www.m5sim.org/warn/55f199fd
+warn: Bad interworking branch address 0x7002.
+For more information see: http://www.m5sim.org/warn/55f199fd
+warn: Bad interworking branch address 0x7002.
+For more information see: http://www.m5sim.org/warn/55f199fd
+warn: Bad interworking branch address 0x7002.
+For more information see: http://www.m5sim.org/warn/55f199fd
+hack: be nice to actually delete the event here
diff --git a/tests/long/00.gzip/ref/arm/linux/o3-timing/simout b/tests/long/00.gzip/ref/arm/linux/o3-timing/simout
new file mode 100755
index 000000000..913163576
--- /dev/null
+++ b/tests/long/00.gzip/ref/arm/linux/o3-timing/simout
@@ -0,0 +1,46 @@
+M5 Simulator System
+
+Copyright (c) 2001-2008
+The Regents of The University of Michigan
+All Rights Reserved
+
+
+M5 compiled Jan 11 2011 18:16:01
+M5 revision b39a8457b332 7816 default ext/o3_regressions.patch qtip tip
+M5 started Jan 12 2011 02:01:01
+M5 executing on u200439-lin.austin.arm.com
+command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/00.gzip/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/fast/long/00.gzip/arm/linux/o3-timing
+Global frequency set at 1000000000000 ticks per second
+info: Entering event queue @ 0. Starting simulation...
+spec_init
+Loading Input Data
+Duplicating 262144 bytes
+Duplicating 524288 bytes
+Input data 1048576 bytes in length
+Compressing Input Data, level 1
+Compressed data 108074 bytes in length
+Uncompressing Data
+Uncompressed data 1048576 bytes in length
+Uncompressed data compared correctly
+Compressing Input Data, level 3
+Compressed data 97831 bytes in length
+Uncompressing Data
+Uncompressed data 1048576 bytes in length
+Uncompressed data compared correctly
+Compressing Input Data, level 5
+Compressed data 83382 bytes in length
+Uncompressing Data
+Uncompressed data 1048576 bytes in length
+Uncompressed data compared correctly
+Compressing Input Data, level 7
+Compressed data 76606 bytes in length
+Uncompressing Data
+Uncompressed data 1048576 bytes in length
+Uncompressed data compared correctly
+Compressing Input Data, level 9
+Compressed data 73189 bytes in length
+Uncompressing Data
+Uncompressed data 1048576 bytes in length
+Uncompressed data compared correctly
+Tested 1MB buffer: OK!
+Exiting @ tick 216988313500 because target called exit()
diff --git a/tests/long/00.gzip/ref/arm/linux/o3-timing/stats.txt b/tests/long/00.gzip/ref/arm/linux/o3-timing/stats.txt
new file mode 100644
index 000000000..c8f41239c
--- /dev/null
+++ b/tests/long/00.gzip/ref/arm/linux/o3-timing/stats.txt
@@ -0,0 +1,494 @@
+
+---------- Begin Simulation Statistics ----------
+host_inst_rate 117336 # Simulator instruction rate (inst/s)
+host_mem_usage 251760 # Number of bytes of host memory used
+host_seconds 5118.46 # Real time elapsed on the host
+host_tick_rate 42393313 # Simulator tick rate (ticks/s)
+sim_freq 1000000000000 # Frequency of simulated ticks
+sim_insts 600581394 # Number of instructions simulated
+sim_seconds 0.216988 # Number of seconds simulated
+sim_ticks 216988313500 # Number of ticks simulated
+system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
+system.cpu.BPredUnit.BTBHits 80605282 # Number of BTB hits
+system.cpu.BPredUnit.BTBLookups 86770000 # Number of BTB lookups
+system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions.
+system.cpu.BPredUnit.condIncorrect 3926724 # Number of conditional branches incorrect
+system.cpu.BPredUnit.condPredicted 92457745 # Number of conditional branches predicted
+system.cpu.BPredUnit.lookups 92457745 # Number of BP lookups
+system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target.
+system.cpu.commit.COM:branches 70067581 # Number of branches committed
+system.cpu.commit.COM:bw_lim_events 7237695 # number cycles where commit BW limit reached
+system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
+system.cpu.commit.COM:committed_per_cycle::samples 415629341 # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::mean 1.444993 # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::stdev 1.803103 # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::0 151329728 36.41% 36.41% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::1 131463070 31.63% 68.04% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::2 59591076 14.34% 82.38% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::3 19300079 4.64% 87.02% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::4 16801344 4.04% 91.06% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::5 14774924 3.55% 94.62% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::6 12865596 3.10% 97.71% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::7 2265829 0.55% 98.26% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::8 7237695 1.74% 100.00% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::total 415629341 # Number of insts commited each cycle
+system.cpu.commit.COM:count 600581394 # Number of instructions committed
+system.cpu.commit.COM:loads 148953025 # Number of loads committed
+system.cpu.commit.COM:membars 0 # Number of memory barriers committed
+system.cpu.commit.COM:refs 219174038 # Number of memory references committed
+system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed
+system.cpu.commit.branchMispredicts 4754911 # The number of times a branch was mispredicted
+system.cpu.commit.commitCommittedInsts 600581394 # The number of committed instructions
+system.cpu.commit.commitNonSpecStalls 3642 # The number of times commit has been forced to stall to communicate backwards
+system.cpu.commit.commitSquashedInsts 121350527 # The number of squashed insts skipped by commit
+system.cpu.committedInsts 600581394 # Number of Instructions Simulated
+system.cpu.committedInsts_total 600581394 # Number of Instructions Simulated
+system.cpu.cpi 0.722594 # CPI: Cycles Per Instruction
+system.cpu.cpi_total 0.722594 # CPI: Total CPI of All Threads
+system.cpu.dcache.ReadReq_accesses 140357692 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_avg_miss_latency 13127.051417 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 7797.439109 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_hits 140121331 # number of ReadReq hits
+system.cpu.dcache.ReadReq_miss_latency 3102723000 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_rate 0.001684 # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_misses 236361 # number of ReadReq misses
+system.cpu.dcache.ReadReq_mshr_hits 40726 # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_miss_latency 1525452000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate 0.001394 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_misses 195635 # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_accesses 69418858 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_avg_miss_latency 17787.356145 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 10360.258061 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_hits 67933393 # number of WriteReq hits
+system.cpu.dcache.WriteReq_miss_latency 26422494996 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_rate 0.021399 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_misses 1485465 # number of WriteReq misses
+system.cpu.dcache.WriteReq_mshr_hits 1237601 # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_miss_latency 2567935004 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_rate 0.003571 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_misses 247864 # number of WriteReq MSHR misses
+system.cpu.dcache.avg_blocked_cycles::no_mshrs 4386.427788 # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
+system.cpu.dcache.avg_refs 469.123189 # Average number of references to valid blocks.
+system.cpu.dcache.blocked::no_mshrs 2188 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_mshrs 9597504 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.cpu.dcache.cache_copies 0 # number of cache copies performed
+system.cpu.dcache.demand_accesses 209776550 # number of demand (read+write) accesses
+system.cpu.dcache.demand_avg_miss_latency 17147.620024 # average overall miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 9229.754755 # average overall mshr miss latency
+system.cpu.dcache.demand_hits 208054724 # number of demand (read+write) hits
+system.cpu.dcache.demand_miss_latency 29525217996 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_rate 0.008208 # miss rate for demand accesses
+system.cpu.dcache.demand_misses 1721826 # number of demand (read+write) misses
+system.cpu.dcache.demand_mshr_hits 1278327 # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_miss_latency 4093387004 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_rate 0.002114 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_misses 443499 # number of demand (read+write) MSHR misses
+system.cpu.dcache.fast_writes 0 # number of fast writes performed
+system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
+system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.dcache.occ_%::0 0.999739 # Average percentage of cache occupancy
+system.cpu.dcache.occ_blocks::0 4094.932542 # Average occupied blocks per context
+system.cpu.dcache.overall_accesses 209776550 # number of overall (read+write) accesses
+system.cpu.dcache.overall_avg_miss_latency 17147.620024 # average overall miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 9229.754755 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
+system.cpu.dcache.overall_hits 208054724 # number of overall hits
+system.cpu.dcache.overall_miss_latency 29525217996 # number of overall miss cycles
+system.cpu.dcache.overall_miss_rate 0.008208 # miss rate for overall accesses
+system.cpu.dcache.overall_misses 1721826 # number of overall misses
+system.cpu.dcache.overall_mshr_hits 1278327 # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_miss_latency 4093387004 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_rate 0.002114 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_misses 443499 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.cpu.dcache.replacements 439401 # number of replacements
+system.cpu.dcache.sampled_refs 443497 # Sample count of references to valid blocks.
+system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.dcache.tagsinuse 4094.932542 # Cycle average of tags in use
+system.cpu.dcache.total_refs 208054727 # Total number of references to valid blocks.
+system.cpu.dcache.warmup_cycle 90722000 # Cycle when the warmup percentage was hit.
+system.cpu.dcache.writebacks 394050 # number of writebacks
+system.cpu.decode.DECODE:BlockedCycles 84141891 # Number of cycles decode is blocked
+system.cpu.decode.DECODE:DecodedInsts 763382279 # Number of instructions handled by decode
+system.cpu.decode.DECODE:IdleCycles 172756991 # Number of cycles decode is idle
+system.cpu.decode.DECODE:RunCycles 145179524 # Number of cycles decode is running
+system.cpu.decode.DECODE:SquashCycles 17468389 # Number of cycles decode is squashing
+system.cpu.decode.DECODE:UnblockCycles 13550935 # Number of cycles decode is unblocking
+system.cpu.dtb.accesses 0 # DTB accesses
+system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
+system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
+system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
+system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
+system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
+system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
+system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
+system.cpu.dtb.hits 0 # DTB hits
+system.cpu.dtb.inst_accesses 0 # ITB inst accesses
+system.cpu.dtb.inst_hits 0 # ITB inst hits
+system.cpu.dtb.inst_misses 0 # ITB inst misses
+system.cpu.dtb.misses 0 # DTB misses
+system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
+system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
+system.cpu.dtb.read_accesses 0 # DTB read accesses
+system.cpu.dtb.read_hits 0 # DTB read hits
+system.cpu.dtb.read_misses 0 # DTB read misses
+system.cpu.dtb.write_accesses 0 # DTB write accesses
+system.cpu.dtb.write_hits 0 # DTB write hits
+system.cpu.dtb.write_misses 0 # DTB write misses
+system.cpu.fetch.Branches 92457745 # Number of branches that fetch encountered
+system.cpu.fetch.CacheLines 75163464 # Number of cache lines fetched
+system.cpu.fetch.Cycles 161721844 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.IcacheSquashes 803289 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.Insts 727645117 # Number of instructions fetch has processed
+system.cpu.fetch.MiscStallCycles 2728 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.SquashCycles 5447650 # Number of cycles fetch has spent squashing
+system.cpu.fetch.branchRate 0.213048 # Number of branch fetches per cycle
+system.cpu.fetch.icacheStallCycles 75163464 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.predictedBranches 80605282 # Number of branches that fetch has predicted taken
+system.cpu.fetch.rate 1.676692 # Number of inst fetches per cycle
+system.cpu.fetch.rateDist::samples 433097730 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean 1.793885 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev 2.871524 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 271377208 62.66% 62.66% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1 26620227 6.15% 68.81% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2 18536414 4.28% 73.09% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3 23464508 5.42% 78.50% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4 11465886 2.65% 81.15% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5 12676535 2.93% 84.08% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6 5122175 1.18% 85.26% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7 7816549 1.80% 87.07% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8 56018228 12.93% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::total 433097730 # Number of instructions fetched each cycle (Total)
+system.cpu.icache.ReadReq_accesses 75163464 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_avg_miss_latency 35391.803279 # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency 34026.104418 # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_hits 75162549 # number of ReadReq hits
+system.cpu.icache.ReadReq_miss_latency 32383500 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_rate 0.000012 # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_misses 915 # number of ReadReq misses
+system.cpu.icache.ReadReq_mshr_hits 168 # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_miss_latency 25417500 # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate 0.000010 # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_misses 747 # number of ReadReq MSHR misses
+system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
+system.cpu.icache.avg_refs 100889.327517 # Average number of references to valid blocks.
+system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
+system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
+system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
+system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.cpu.icache.cache_copies 0 # number of cache copies performed
+system.cpu.icache.demand_accesses 75163464 # number of demand (read+write) accesses
+system.cpu.icache.demand_avg_miss_latency 35391.803279 # average overall miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency 34026.104418 # average overall mshr miss latency
+system.cpu.icache.demand_hits 75162549 # number of demand (read+write) hits
+system.cpu.icache.demand_miss_latency 32383500 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_rate 0.000012 # miss rate for demand accesses
+system.cpu.icache.demand_misses 915 # number of demand (read+write) misses
+system.cpu.icache.demand_mshr_hits 168 # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_miss_latency 25417500 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_rate 0.000010 # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_misses 747 # number of demand (read+write) MSHR misses
+system.cpu.icache.fast_writes 0 # number of fast writes performed
+system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
+system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.icache.occ_%::0 0.323287 # Average percentage of cache occupancy
+system.cpu.icache.occ_blocks::0 662.091545 # Average occupied blocks per context
+system.cpu.icache.overall_accesses 75163464 # number of overall (read+write) accesses
+system.cpu.icache.overall_avg_miss_latency 35391.803279 # average overall miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency 34026.104418 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
+system.cpu.icache.overall_hits 75162549 # number of overall hits
+system.cpu.icache.overall_miss_latency 32383500 # number of overall miss cycles
+system.cpu.icache.overall_miss_rate 0.000012 # miss rate for overall accesses
+system.cpu.icache.overall_misses 915 # number of overall misses
+system.cpu.icache.overall_mshr_hits 168 # number of overall MSHR hits
+system.cpu.icache.overall_mshr_miss_latency 25417500 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_rate 0.000010 # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_misses 747 # number of overall MSHR misses
+system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
+system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.cpu.icache.replacements 23 # number of replacements
+system.cpu.icache.sampled_refs 745 # Sample count of references to valid blocks.
+system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.icache.tagsinuse 662.091545 # Cycle average of tags in use
+system.cpu.icache.total_refs 75162549 # Total number of references to valid blocks.
+system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu.icache.writebacks 0 # number of writebacks
+system.cpu.idleCycles 878898 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.iew.EXEC:branches 74261584 # Number of branches executed
+system.cpu.iew.EXEC:nop 0 # number of nop insts executed
+system.cpu.iew.EXEC:rate 1.487821 # Inst execution rate
+system.cpu.iew.EXEC:refs 240772759 # number of memory reference insts executed
+system.cpu.iew.EXEC:stores 74373435 # Number of stores executed
+system.cpu.iew.EXEC:swp 0 # number of swp insts executed
+system.cpu.iew.WB:consumers 747728848 # num instructions consuming a value
+system.cpu.iew.WB:count 638555092 # cumulative count of insts written-back
+system.cpu.iew.WB:fanout 0.593985 # average fanout of values written-back
+system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
+system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
+system.cpu.iew.WB:producers 444140092 # num instructions producing a value
+system.cpu.iew.WB:rate 1.471404 # insts written-back per cycle
+system.cpu.iew.WB:sent 640268738 # cumulative count of insts sent to commit
+system.cpu.iew.branchMispredicts 5263099 # Number of branch mispredicts detected at execute
+system.cpu.iew.iewBlockCycles 938806 # Number of cycles IEW is blocking
+system.cpu.iew.iewDispLoadInsts 184696678 # Number of dispatched load instructions
+system.cpu.iew.iewDispNonSpecInsts 3886 # Number of dispatched non-speculative instructions
+system.cpu.iew.iewDispSquashedInsts 3056895 # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispStoreInsts 88578802 # Number of dispatched store instructions
+system.cpu.iew.iewDispatchedInsts 721929575 # Number of instructions dispatched to IQ
+system.cpu.iew.iewExecLoadInsts 166399324 # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts 7744433 # Number of squashed instructions skipped in execute
+system.cpu.iew.iewExecutedInsts 645679694 # Number of executed instructions
+system.cpu.iew.iewIQFullEvents 15541 # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
+system.cpu.iew.iewLSQFullEvents 10568 # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.iewSquashCycles 17468389 # Number of cycles IEW is squashing
+system.cpu.iew.iewUnblockCycles 68840 # Number of cycles IEW is unblocking
+system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
+system.cpu.iew.lsq.thread.0.cacheBlocked 8986 # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread.0.forwLoads 24659910 # Number of loads that had data forwarded from stores
+system.cpu.iew.lsq.thread.0.ignoredResponses 40290 # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address
+system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
+system.cpu.iew.lsq.thread.0.memOrderViolation 927620 # Number of memory ordering violations
+system.cpu.iew.lsq.thread.0.rescheduledLoads 15164 # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread.0.squashedLoads 35743652 # Number of loads squashed
+system.cpu.iew.lsq.thread.0.squashedStores 18357789 # Number of stores squashed
+system.cpu.iew.memOrderViolationEvents 927620 # Number of memory order violations
+system.cpu.iew.predictedNotTakenIncorrect 1456086 # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.predictedTakenIncorrect 3807013 # Number of branches that were predicted taken incorrectly
+system.cpu.ipc 1.383903 # IPC: Instructions Per Cycle
+system.cpu.ipc_total 1.383903 # IPC: Total IPC of All Threads
+system.cpu.iq.ISSUE:FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::IntAlu 408584049 62.53% 62.53% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::IntMult 6689 0.00% 62.53% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 62.53% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::FloatAdd 0 0.00% 62.53% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 62.53% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 62.53% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 62.53% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 62.53% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 62.53% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdAdd 0 0.00% 62.53% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdAddAcc 0 0.00% 62.53% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdAlu 0 0.00% 62.53% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdCmp 0 0.00% 62.53% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdCvt 0 0.00% 62.53% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdMisc 0 0.00% 62.53% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdMult 0 0.00% 62.53% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdMultAcc 0 0.00% 62.53% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdShift 0 0.00% 62.53% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdShiftAcc 0 0.00% 62.53% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdSqrt 0 0.00% 62.53% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdFloatAdd 0 0.00% 62.53% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdFloatAlu 0 0.00% 62.53% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdFloatCmp 0 0.00% 62.53% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdFloatCvt 0 0.00% 62.53% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdFloatDiv 0 0.00% 62.53% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdFloatMisc 3 0.00% 62.53% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdFloatMult 0 0.00% 62.53% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdFloatMultAcc 0 0.00% 62.53% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdFloatSqrt 0 0.00% 62.53% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::MemRead 168909832 25.85% 88.38% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::MemWrite 75923554 11.62% 100.00% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::total 653424127 # Type of FU issued
+system.cpu.iq.ISSUE:fu_busy_cnt 7689778 # FU busy when requested
+system.cpu.iq.ISSUE:fu_busy_rate 0.011768 # FU busy rate (busy events/executed inst)
+system.cpu.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::IntAlu 110226 1.43% 1.43% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 1.43% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 1.43% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 1.43% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 1.43% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 1.43% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 1.43% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 1.43% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 1.43% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdAdd 0 0.00% 1.43% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdAddAcc 0 0.00% 1.43% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdAlu 0 0.00% 1.43% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdCmp 0 0.00% 1.43% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdCvt 0 0.00% 1.43% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdMisc 0 0.00% 1.43% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdMult 0 0.00% 1.43% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdMultAcc 0 0.00% 1.43% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdShift 0 0.00% 1.43% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdShiftAcc 0 0.00% 1.43% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdSqrt 0 0.00% 1.43% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdFloatAdd 0 0.00% 1.43% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdFloatAlu 0 0.00% 1.43% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdFloatCmp 0 0.00% 1.43% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdFloatCvt 0 0.00% 1.43% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdFloatDiv 0 0.00% 1.43% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdFloatMisc 0 0.00% 1.43% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdFloatMult 0 0.00% 1.43% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdFloatMultAcc 0 0.00% 1.43% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdFloatSqrt 0 0.00% 1.43% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::MemRead 7362915 95.75% 97.18% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::MemWrite 216637 2.82% 100.00% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
+system.cpu.iq.ISSUE:issued_per_cycle::samples 433097730 # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::mean 1.508722 # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.485636 # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::0 131709381 30.41% 30.41% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::1 125173843 28.90% 59.31% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::2 78416744 18.11% 77.42% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::3 46404818 10.71% 88.13% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::4 32896297 7.60% 95.73% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::5 12946022 2.99% 98.72% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::6 3892650 0.90% 99.62% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::7 732656 0.17% 99.79% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::8 925319 0.21% 100.00% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::total 433097730 # Number of insts issued each cycle
+system.cpu.iq.ISSUE:rate 1.505667 # Inst issue rate
+system.cpu.iq.iqInstsAdded 721925689 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqInstsIssued 653424127 # Number of instructions issued
+system.cpu.iq.iqNonSpecInstsAdded 3886 # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqSquashedInstsExamined 120964345 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedInstsIssued 625992 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedNonSpecRemoved 244 # Number of squashed non-spec instructions that were removed
+system.cpu.iq.iqSquashedOperandsExamined 239956902 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.itb.accesses 0 # DTB accesses
+system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
+system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
+system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
+system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
+system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
+system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
+system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
+system.cpu.itb.hits 0 # DTB hits
+system.cpu.itb.inst_accesses 0 # ITB inst accesses
+system.cpu.itb.inst_hits 0 # ITB inst hits
+system.cpu.itb.inst_misses 0 # ITB inst misses
+system.cpu.itb.misses 0 # DTB misses
+system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
+system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
+system.cpu.itb.read_accesses 0 # DTB read accesses
+system.cpu.itb.read_hits 0 # DTB read hits
+system.cpu.itb.read_misses 0 # DTB read misses
+system.cpu.itb.write_accesses 0 # DTB write accesses
+system.cpu.itb.write_hits 0 # DTB write hits
+system.cpu.itb.write_misses 0 # DTB write misses
+system.cpu.l2cache.ReadExReq_accesses 247865 # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_avg_miss_latency 34472.327689 # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31273.618950 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_hits 189395 # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_miss_latency 2015597000 # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_rate 0.235895 # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_misses 58470 # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_mshr_miss_latency 1828568500 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.235895 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_misses 58470 # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadReq_accesses 196377 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_avg_miss_latency 34258.171034 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31117.674945 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_hits 163670 # number of ReadReq hits
+system.cpu.l2cache.ReadReq_miss_latency 1120482000 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_rate 0.166552 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_misses 32707 # number of ReadReq misses
+system.cpu.l2cache.ReadReq_mshr_hits 11 # number of ReadReq MSHR hits
+system.cpu.l2cache.ReadReq_mshr_miss_latency 1017423500 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate 0.166496 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_misses 32696 # number of ReadReq MSHR misses
+system.cpu.l2cache.UpgradeReq_accesses 1 # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31000 # average UpgradeReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_misses 1 # number of UpgradeReq misses
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency 31000 # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_misses 1 # number of UpgradeReq MSHR misses
+system.cpu.l2cache.Writeback_accesses 394050 # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_hits 394050 # number of Writeback hits
+system.cpu.l2cache.avg_blocked_cycles::no_mshrs 6190.332326 # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
+system.cpu.l2cache.avg_refs 4.731748 # Average number of references to valid blocks.
+system.cpu.l2cache.blocked::no_mshrs 331 # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
+system.cpu.l2cache.blocked_cycles::no_mshrs 2049000 # number of cycles access was blocked
+system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.cpu.l2cache.cache_copies 0 # number of cache copies performed
+system.cpu.l2cache.demand_accesses 444242 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_avg_miss_latency 34395.505445 # average overall miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency 31217.690806 # average overall mshr miss latency
+system.cpu.l2cache.demand_hits 353065 # number of demand (read+write) hits
+system.cpu.l2cache.demand_miss_latency 3136079000 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_rate 0.205242 # miss rate for demand accesses
+system.cpu.l2cache.demand_misses 91177 # number of demand (read+write) misses
+system.cpu.l2cache.demand_mshr_hits 11 # number of demand (read+write) MSHR hits
+system.cpu.l2cache.demand_mshr_miss_latency 2845992000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_rate 0.205217 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_misses 91166 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.fast_writes 0 # number of fast writes performed
+system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
+system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.l2cache.occ_%::0 0.056947 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_%::1 0.488639 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_blocks::0 1866.034390 # Average occupied blocks per context
+system.cpu.l2cache.occ_blocks::1 16011.711399 # Average occupied blocks per context
+system.cpu.l2cache.overall_accesses 444242 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_avg_miss_latency 34395.505445 # average overall miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency 31217.690806 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
+system.cpu.l2cache.overall_hits 353065 # number of overall hits
+system.cpu.l2cache.overall_miss_latency 3136079000 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_rate 0.205242 # miss rate for overall accesses
+system.cpu.l2cache.overall_misses 91177 # number of overall misses
+system.cpu.l2cache.overall_mshr_hits 11 # number of overall MSHR hits
+system.cpu.l2cache.overall_mshr_miss_latency 2845992000 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_rate 0.205217 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_misses 91166 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.cpu.l2cache.replacements 72987 # number of replacements
+system.cpu.l2cache.sampled_refs 88484 # Sample count of references to valid blocks.
+system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.l2cache.tagsinuse 17877.745789 # Cycle average of tags in use
+system.cpu.l2cache.total_refs 418684 # Total number of references to valid blocks.
+system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.writebacks 58152 # number of writebacks
+system.cpu.memDep0.conflictingLoads 56143840 # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores 33466008 # Number of conflicting stores.
+system.cpu.memDep0.insertedLoads 184696678 # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores 88578802 # Number of stores inserted to the mem dependence unit.
+system.cpu.numCycles 433976628 # number of cpu cycles simulated
+system.cpu.rename.RENAME:BlockCycles 12394432 # Number of cycles rename is blocking
+system.cpu.rename.RENAME:CommittedMaps 469246940 # Number of HB maps that are committed
+system.cpu.rename.RENAME:IQFullEvents 63310884 # Number of times rename has blocked due to IQ full
+system.cpu.rename.RENAME:IdleCycles 190432951 # Number of cycles rename is idle
+system.cpu.rename.RENAME:LSQFullEvents 3181742 # Number of times rename has blocked due to LSQ full
+system.cpu.rename.RENAME:ROBFullEvents 1 # Number of times rename has blocked due to ROB full
+system.cpu.rename.RENAME:RenameLookups 2146132338 # Number of register rename lookups that rename has made
+system.cpu.rename.RENAME:RenamedInsts 749362118 # Number of instructions processed by rename
+system.cpu.rename.RENAME:RenamedOperands 579635257 # Number of destination operands rename has renamed
+system.cpu.rename.RENAME:RunCycles 140765492 # Number of cycles rename is running
+system.cpu.rename.RENAME:SquashCycles 17468389 # Number of cycles rename is squashing
+system.cpu.rename.RENAME:UnblockCycles 71980169 # Number of cycles rename is unblocking
+system.cpu.rename.RENAME:UndoneMaps 110388314 # Number of HB maps that are undone due to squashing
+system.cpu.rename.RENAME:serializeStallCycles 56297 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RENAME:serializingInsts 3959 # count of serializing insts renamed
+system.cpu.rename.RENAME:skidInsts 128598467 # count of insts added to the skid buffer
+system.cpu.rename.RENAME:tempSerializingInsts 3953 # count of temporary serializing insts renamed
+system.cpu.timesIdled 36486 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.workload.PROG:num_syscalls 48 # Number of system calls
+
+---------- End Simulation Statistics ----------