diff options
| author | Steve Reinhardt <steve.reinhardt@amd.com> | 2010-09-21 23:07:35 -0700 |
|---|---|---|
| committer | Steve Reinhardt <steve.reinhardt@amd.com> | 2010-09-21 23:07:35 -0700 |
| commit | 13a15c55a40e86e5f3948a387fb5e50b9a1cdccf (patch) | |
| tree | 762286677b3170cf9a7fb348f44e74a276230d6c /tests/long/00.gzip/ref/arm/linux | |
| parent | e9185363804489ce2b84d50fe77ed94f3a5f1e01 (diff) | |
| download | gem5-13a15c55a40e86e5f3948a387fb5e50b9a1cdccf.tar.xz | |
stats: update stats for previous cset
Coherence protocol change basically got rid
of UpgradeReqs in L2 caches, other minor
related cache stat changes.
Diffstat (limited to 'tests/long/00.gzip/ref/arm/linux')
3 files changed, 91 insertions, 102 deletions
diff --git a/tests/long/00.gzip/ref/arm/linux/simple-timing/config.ini b/tests/long/00.gzip/ref/arm/linux/simple-timing/config.ini index 4bef17201..19272883f 100644 --- a/tests/long/00.gzip/ref/arm/linux/simple-timing/config.ini +++ b/tests/long/00.gzip/ref/arm/linux/simple-timing/config.ini @@ -157,7 +157,7 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/cpu2000/binaries/arm/linux/gzip +executable=/home/stever/m5/dist/cpu2000/binaries/arm/linux/gzip gid=100 input=cin max_stack_size=67108864 diff --git a/tests/long/00.gzip/ref/arm/linux/simple-timing/simout b/tests/long/00.gzip/ref/arm/linux/simple-timing/simout index b26d693cf..107f995a8 100755 --- a/tests/long/00.gzip/ref/arm/linux/simple-timing/simout +++ b/tests/long/00.gzip/ref/arm/linux/simple-timing/simout @@ -1,5 +1,3 @@ -Redirecting stdout to build/ARM_SE/tests/opt/long/00.gzip/arm/linux/simple-timing/simout -Redirecting stderr to build/ARM_SE/tests/opt/long/00.gzip/arm/linux/simple-timing/simerr M5 Simulator System Copyright (c) 2001-2008 @@ -7,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Aug 26 2010 13:52:30 -M5 revision 85cafc6ccb42 7662 default qtip tip sc-fail-fix -M5 started Aug 26 2010 13:54:54 -M5 executing on zizzer +M5 compiled Sep 20 2010 15:04:50 +M5 revision 0c4a7d867247 7686 default qtip print-identical tip +M5 started Sep 20 2010 15:05:18 +M5 executing on phenom command line: build/ARM_SE/m5.opt -d build/ARM_SE/tests/opt/long/00.gzip/arm/linux/simple-timing -re tests/run.py build/ARM_SE/tests/opt/long/00.gzip/arm/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... @@ -45,4 +43,4 @@ Uncompressing Data Uncompressed data 1048576 bytes in length Uncompressed data compared correctly Tested 1MB buffer: OK! -Exiting @ tick 807517408000 because target called exit() +Exiting @ tick 796759936000 because target called exit() diff --git a/tests/long/00.gzip/ref/arm/linux/simple-timing/stats.txt b/tests/long/00.gzip/ref/arm/linux/simple-timing/stats.txt index 4b4cf244a..11f65fd19 100644 --- a/tests/long/00.gzip/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/00.gzip/ref/arm/linux/simple-timing/stats.txt @@ -1,33 +1,33 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1492183 # Simulator instruction rate (inst/s) -host_mem_usage 211112 # Number of bytes of host memory used -host_seconds 401.17 # Real time elapsed on the host -host_tick_rate 2012902303 # Simulator tick rate (ticks/s) +host_inst_rate 1338185 # Simulator instruction rate (inst/s) +host_mem_usage 196956 # Number of bytes of host memory used +host_seconds 447.34 # Real time elapsed on the host +host_tick_rate 1781116972 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 598619824 # Number of instructions simulated -sim_seconds 0.807517 # Number of seconds simulated -sim_ticks 807517408000 # Number of ticks simulated +sim_seconds 0.796760 # Number of seconds simulated +sim_ticks 796759936000 # Number of ticks simulated system.cpu.dcache.ReadReq_accesses 147793610 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 21105.418688 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 18105.418688 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_miss_latency 20842.812219 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 17842.812219 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_hits 147603767 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 4006716000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency 3956862000 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_rate 0.001285 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_misses 189843 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_miss_latency 3437187000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency 3387333000 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate 0.001285 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_misses 189843 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_accesses 69418858 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 54322.323841 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 51322.323841 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 69111608 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 16690534000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.004426 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 307250 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_miss_latency 15768784000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate 0.004426 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 307250 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_avg_miss_latency 23909.028529 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 20909.028529 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 69171110 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 5923414000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.003569 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 247748 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_miss_latency 5180170000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate 0.003569 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_misses 247748 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.dcache.avg_refs 495.382394 # Average number of references to valid blocks. @@ -37,42 +37,42 @@ system.cpu.dcache.blocked_cycles::no_mshrs 0 # system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.demand_accesses 217212468 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 41636.575047 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 38636.575047 # average overall mshr miss latency -system.cpu.dcache.demand_hits 216715375 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 20697250000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.002289 # miss rate for demand accesses -system.cpu.dcache.demand_misses 497093 # number of demand (read+write) misses +system.cpu.dcache.demand_avg_miss_latency 22578.791611 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 19578.791611 # average overall mshr miss latency +system.cpu.dcache.demand_hits 216774877 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 9880276000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.002015 # miss rate for demand accesses +system.cpu.dcache.demand_misses 437591 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 19205971000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.002289 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 497093 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_miss_latency 8567503000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.002015 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses 437591 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.occ_%::0 0.999572 # Average percentage of cache occupancy -system.cpu.dcache.occ_blocks::0 4094.246847 # Average occupied blocks per context +system.cpu.dcache.occ_%::0 0.999566 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::0 4094.223177 # Average occupied blocks per context system.cpu.dcache.overall_accesses 217212468 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 41636.575047 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 38636.575047 # average overall mshr miss latency +system.cpu.dcache.overall_avg_miss_latency 22578.791611 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 19578.791611 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 216715375 # number of overall hits -system.cpu.dcache.overall_miss_latency 20697250000 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.002289 # miss rate for overall accesses -system.cpu.dcache.overall_misses 497093 # number of overall misses +system.cpu.dcache.overall_hits 216774877 # number of overall hits +system.cpu.dcache.overall_miss_latency 9880276000 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.002015 # miss rate for overall accesses +system.cpu.dcache.overall_misses 437591 # number of overall misses system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 19205971000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.002289 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 497093 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_miss_latency 8567503000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.002015 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses 437591 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.dcache.replacements 433495 # number of replacements system.cpu.dcache.sampled_refs 437591 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 4094.246847 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 4094.223177 # Cycle average of tags in use system.cpu.dcache.total_refs 216774877 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 537003000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.writebacks 305501 # number of writebacks +system.cpu.dcache.writebacks 392389 # number of writebacks system.cpu.dtb.accesses 0 # DTB accesses system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses @@ -114,8 +114,8 @@ system.cpu.icache.demand_mshr_misses 643 # nu system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.occ_%::0 0.282055 # Average percentage of cache occupancy -system.cpu.icache.occ_blocks::0 577.648910 # Average occupied blocks per context +system.cpu.icache.occ_%::0 0.282094 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::0 577.728453 # Average occupied blocks per context system.cpu.icache.overall_accesses 570070553 # number of overall (read+write) accesses system.cpu.icache.overall_avg_miss_latency 54236.391913 # average overall miss latency system.cpu.icache.overall_avg_mshr_miss_latency 51236.391913 # average overall mshr miss latency @@ -133,7 +133,7 @@ system.cpu.icache.overall_mshr_uncacheable_misses 0 system.cpu.icache.replacements 12 # number of replacements system.cpu.icache.sampled_refs 643 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 577.648910 # Cycle average of tags in use +system.cpu.icache.tagsinuse 577.728453 # Cycle average of tags in use system.cpu.icache.total_refs 570069910 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks @@ -150,37 +150,28 @@ system.cpu.itb.write_misses 0 # DT system.cpu.l2cache.ReadExReq_accesses 247748 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_hits 12273 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_miss_latency 12244700000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_rate 0.950462 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_misses 235475 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency 9419000000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.950462 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_misses 235475 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_hits 189297 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_miss_latency 3039452000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_rate 0.235929 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_misses 58451 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency 2338040000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.235929 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_misses 58451 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadReq_accesses 190486 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_hits 157753 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 1702116000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.171839 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 32733 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 1309320000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.171839 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 32733 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_accesses 59502 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_avg_miss_latency 52000 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_miss_latency 3094104000 # number of UpgradeReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_misses 59502 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_mshr_miss_latency 2380080000 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_misses 59502 # number of UpgradeReq MSHR misses -system.cpu.l2cache.Writeback_accesses 305501 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_hits 305501 # number of Writeback hits +system.cpu.l2cache.ReadReq_hits 158940 # number of ReadReq hits +system.cpu.l2cache.ReadReq_miss_latency 1640392000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.165608 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 31546 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 1261840000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.165608 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 31546 # number of ReadReq MSHR misses +system.cpu.l2cache.Writeback_accesses 392389 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_hits 392389 # number of Writeback hits system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 3.379196 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 4.718118 # Average number of references to valid blocks. system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked @@ -189,44 +180,44 @@ system.cpu.l2cache.cache_copies 0 # nu system.cpu.l2cache.demand_accesses 438234 # number of demand (read+write) accesses system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency -system.cpu.l2cache.demand_hits 170026 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 13946816000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.612020 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 268208 # number of demand (read+write) misses +system.cpu.l2cache.demand_hits 348237 # number of demand (read+write) hits +system.cpu.l2cache.demand_miss_latency 4679844000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.205363 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 89997 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 10728320000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.612020 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 268208 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_miss_latency 3599880000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.205363 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 89997 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.occ_%::0 0.050080 # Average percentage of cache occupancy -system.cpu.l2cache.occ_%::1 0.453180 # Average percentage of cache occupancy -system.cpu.l2cache.occ_blocks::0 1641.035711 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 14849.786647 # Average occupied blocks per context +system.cpu.l2cache.occ_%::0 0.053819 # Average percentage of cache occupancy +system.cpu.l2cache.occ_%::1 0.492601 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::0 1763.554655 # Average occupied blocks per context +system.cpu.l2cache.occ_blocks::1 16141.554862 # Average occupied blocks per context system.cpu.l2cache.overall_accesses 438234 # number of overall (read+write) accesses system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.l2cache.overall_hits 170026 # number of overall hits -system.cpu.l2cache.overall_miss_latency 13946816000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.612020 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 268208 # number of overall misses +system.cpu.l2cache.overall_hits 348237 # number of overall hits +system.cpu.l2cache.overall_miss_latency 4679844000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.205363 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 89997 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 10728320000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.612020 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 268208 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_miss_latency 3599880000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.205363 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 89997 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.replacements 80841 # number of replacements -system.cpu.l2cache.sampled_refs 96272 # Sample count of references to valid blocks. +system.cpu.l2cache.replacements 71809 # number of replacements +system.cpu.l2cache.sampled_refs 87292 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 16490.822357 # Cycle average of tags in use -system.cpu.l2cache.total_refs 325322 # Total number of references to valid blocks. +system.cpu.l2cache.tagsinuse 17905.109517 # Cycle average of tags in use +system.cpu.l2cache.total_refs 411854 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.writebacks 60805 # number of writebacks +system.cpu.l2cache.writebacks 57886 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 1615034816 # number of cpu cycles simulated +system.cpu.numCycles 1593519872 # number of cpu cycles simulated system.cpu.num_insts 598619824 # Number of instructions executed system.cpu.num_refs 219174038 # Number of memory references system.cpu.workload.PROG:num_syscalls 48 # Number of system calls |