tests: updates for stat name change

2 files changed, 16 insertions, 16 deletions

diff --git a/tests/long/00.gzip/ref/arm/linux/o3-timing/simout b/tests/long/00.gzip/ref/arm/linux/o3-timing/simout
index facf2b9b0..408898e50 100755
--- a/tests/long/00.gzip/ref/arm/linux/o3-timing/simout
+++ b/tests/long/00.gzip/ref/arm/linux/o3-timing/simout
@@ -5,8 +5,8 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Apr 19 2011 12:47:10
-M5 started Apr 19 2011 12:47:12
+M5 compiled Apr 21 2011 12:05:01
+M5 started Apr 21 2011 14:06:31
 M5 executing on maize
 command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/00.gzip/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/fast/long/00.gzip/arm/linux/o3-timing
 Global frequency set at 1000000000000 ticks per second
diff --git a/tests/long/00.gzip/ref/arm/linux/o3-timing/stats.txt b/tests/long/00.gzip/ref/arm/linux/o3-timing/stats.txt
index 5fb65989e..cd3ca8de5 100644
--- a/tests/long/00.gzip/ref/arm/linux/o3-timing/stats.txt
+++ b/tests/long/00.gzip/ref/arm/linux/o3-timing/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                 283332                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 214996                       # Number of bytes of host memory used
-host_seconds                                  2125.99                       # Real time elapsed on the host
-host_tick_rate                               92433779                       # Simulator tick rate (ticks/s)
+host_inst_rate                                 169360                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 217476                       # Number of bytes of host memory used
+host_seconds                                  3556.69                       # Real time elapsed on the host
+host_tick_rate                               55251704                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                   602359865                       # Number of instructions simulated
 sim_seconds                                  0.196513                       # Number of seconds simulated
@@ -265,16 +265,16 @@ system.cpu.iew.iewIdleCycles                        0                       # Nu
 system.cpu.iew.iewLSQFullEvents                  3721                       # Number of times the LSQ has become full, causing a stall
 system.cpu.iew.iewSquashCycles               12871984                       # Number of cycles IEW is squashing
 system.cpu.iew.iewUnblockCycles                 65726                       # Number of cycles IEW is unblocking
-system.cpu.iew.lsq.thread.0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread.0.cacheBlocked         8982                       # Number of times an access to memory failed due to the cache being blocked
-system.cpu.iew.lsq.thread.0.forwLoads        25082678                       # Number of loads that had data forwarded from stores
-system.cpu.iew.lsq.thread.0.ignoredResponses        87734                       # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread.0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread.0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
-system.cpu.iew.lsq.thread.0.memOrderViolation       611520                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread.0.rescheduledLoads        15892                       # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread.0.squashedLoads     27153747                       # Number of loads squashed
-system.cpu.iew.lsq.thread.0.squashedStores     11966835                       # Number of stores squashed
+system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
+system.cpu.iew.lsq.thread0.cacheBlocked          8982                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.forwLoads         25082678                       # Number of loads that had data forwarded from stores
+system.cpu.iew.lsq.thread0.ignoredResponses        87734                       # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
+system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
+system.cpu.iew.lsq.thread0.memOrderViolation       611520                       # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.rescheduledLoads        15892                       # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.squashedLoads     27153747                       # Number of loads squashed
+system.cpu.iew.lsq.thread0.squashedStores     11966835                       # Number of stores squashed
 system.cpu.iew.memOrderViolationEvents         611520                       # Number of memory order violations
 system.cpu.iew.predictedNotTakenIncorrect       628522                       # Number of branches that were predicted not taken incorrectly
 system.cpu.iew.predictedTakenIncorrect        3676919                       # Number of branches that were predicted taken incorrectly