Update of reference outputs. SPARC_SE o3 gzip didn't have reference outputs, mcf has a reduced input size, and most of the other changes are for a change in how branch mispredicts work which makes things more accurate.

--HG--
extra : convert_revision : 33ad6a220945b344d2fc5c6abef8e67467e0c0ec

1 files changed, 423 insertions, 0 deletions

diff --git a/tests/long/00.gzip/ref/sparc/linux/o3-timing/m5stats.txt b/tests/long/00.gzip/ref/sparc/linux/o3-timing/m5stats.txt
new file mode 100644
index 000000000..929354b82
--- /dev/null
+++ b/tests/long/00.gzip/ref/sparc/linux/o3-timing/m5stats.txt
@@ -0,0 +1,423 @@
+
+---------- Begin Simulation Statistics ----------
+global.BPredUnit.BTBCorrect                         0                       # Number of correct BTB predictions (this stat may not work properly.
+global.BPredUnit.BTBHits                    155497873                       # Number of BTB hits
+global.BPredUnit.BTBLookups                 176569029                       # Number of BTB lookups
+global.BPredUnit.RASInCorrect                       0                       # Number of incorrect RAS predictions.
+global.BPredUnit.condIncorrect               90327270                       # Number of conditional branches incorrect
+global.BPredUnit.condPredicted              223339092                       # Number of conditional branches predicted
+global.BPredUnit.lookups                    223339092                       # Number of BP lookups
+global.BPredUnit.usedRAS                            0                       # Number of times the RAS was used to get a target.
+host_inst_rate                                  54106                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 156124                       # Number of bytes of host memory used
+host_seconds                                 27529.37                       # Real time elapsed on the host
+host_tick_rate                               45674334                       # Simulator tick rate (ticks/s)
+memdepunit.memDep.conflictingLoads          464625781                       # Number of conflicting loads.
+memdepunit.memDep.conflictingStores         155659586                       # Number of conflicting stores.
+memdepunit.memDep.insertedLoads             751805606                       # Number of loads inserted to the mem dependence unit.
+memdepunit.memDep.insertedStores            305482201                       # Number of stores inserted to the mem dependence unit.
+sim_freq                                 1000000000000                       # Frequency of simulated ticks
+sim_insts                                  1489514762                       # Number of instructions simulated
+sim_seconds                                  1.257386                       # Number of seconds simulated
+sim_ticks                                1257385552000                       # Number of ticks simulated
+system.cpu.commit.COM:branches               86246390                       # Number of branches committed
+system.cpu.commit.COM:bw_lim_events           9313657                       # number cycles where commit BW limit reached
+system.cpu.commit.COM:bw_limited                    0                       # number of insts not committed due to BW limits
+system.cpu.commit.COM:committed_per_cycle.start_dist                     # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle.samples   2273477268                      
+system.cpu.commit.COM:committed_per_cycle.min_value            0                      
+                               0   1413600532   6217.79%           
+                               1    557883273   2453.88%           
+                               2    123364539    542.62%           
+                               3    120963543    532.06%           
+                               4     18884040     83.06%           
+                               5     12171132     53.54%           
+                               6      9965158     43.83%           
+                               7      7331394     32.25%           
+                               8      9313657     40.97%           
+system.cpu.commit.COM:committed_per_cycle.max_value            8                      
+system.cpu.commit.COM:committed_per_cycle.end_dist
+
+system.cpu.commit.COM:count                1489514762                       # Number of instructions committed
+system.cpu.commit.COM:loads                 402511689                       # Number of loads committed
+system.cpu.commit.COM:membars                   51356                       # Number of memory barriers committed
+system.cpu.commit.COM:refs                  569359657                       # Number of memory references committed
+system.cpu.commit.COM:swp_count                     0                       # Number of s/w prefetches committed
+system.cpu.commit.branchMispredicts          90327270                       # The number of times a branch was mispredicted
+system.cpu.commit.commitCommittedInsts     1489514762                       # The number of committed instructions
+system.cpu.commit.commitNonSpecStalls         2243499                       # The number of times commit has been forced to stall to communicate backwards
+system.cpu.commit.commitSquashedInsts      1399513618                       # The number of squashed insts skipped by commit
+system.cpu.committedInsts                  1489514762                       # Number of Instructions Simulated
+system.cpu.committedInsts_total            1489514762                       # Number of Instructions Simulated
+system.cpu.cpi                               1.688316                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         1.688316                       # CPI: Total CPI of All Threads
+system.cpu.dcache.ReadReq_accesses          431095835                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_avg_miss_latency  2842.252413                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency  2392.500580                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_hits              430168385                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_miss_latency     2636047000                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_rate          0.002151                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_misses               927450                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_mshr_hits            694672                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_miss_latency    556921500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate     0.000540                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_misses          232778                       # number of ReadReq MSHR misses
+system.cpu.dcache.SwapReq_accesses               1326                       # number of SwapReq accesses(hits+misses)
+system.cpu.dcache.SwapReq_avg_miss_latency         3500                       # average SwapReq miss latency
+system.cpu.dcache.SwapReq_avg_mshr_miss_latency         2500                       # average SwapReq mshr miss latency
+system.cpu.dcache.SwapReq_hits                   1319                       # number of SwapReq hits
+system.cpu.dcache.SwapReq_miss_latency          24500                       # number of SwapReq miss cycles
+system.cpu.dcache.SwapReq_miss_rate          0.005279                       # miss rate for SwapReq accesses
+system.cpu.dcache.SwapReq_misses                    7                       # number of SwapReq misses
+system.cpu.dcache.SwapReq_mshr_miss_latency        17500                       # number of SwapReq MSHR miss cycles
+system.cpu.dcache.SwapReq_mshr_miss_rate     0.005279                       # mshr miss rate for SwapReq accesses
+system.cpu.dcache.SwapReq_mshr_misses               7                       # number of SwapReq MSHR misses
+system.cpu.dcache.WriteReq_accesses         166846642                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_avg_miss_latency  3889.592412                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency  3171.120393                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_hits             165155866                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_miss_latency    6576429500                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_rate         0.010134                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_misses             1690776                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_mshr_hits          1420478                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_miss_latency    857147500                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_rate     0.001620                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_misses         270298                       # number of WriteReq MSHR misses
+system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0>                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0>                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_refs                1183.354576                       # Average number of references to valid blocks.
+system.cpu.dcache.blocked_no_mshrs                  0                       # number of cycles access was blocked
+system.cpu.dcache.blocked_no_targets                0                       # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles_no_mshrs            0                       # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles_no_targets            0                       # number of cycles access was blocked
+system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
+system.cpu.dcache.demand_accesses           597942477                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_avg_miss_latency  3518.594842                       # average overall miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency  2810.845677                       # average overall mshr miss latency
+system.cpu.dcache.demand_hits               595324251                       # number of demand (read+write) hits
+system.cpu.dcache.demand_miss_latency      9212476500                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_rate           0.004379                       # miss rate for demand accesses
+system.cpu.dcache.demand_misses               2618226                       # number of demand (read+write) misses
+system.cpu.dcache.demand_mshr_hits            2115150                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_miss_latency   1414069000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_rate      0.000841                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_misses           503076                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
+system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
+system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
+system.cpu.dcache.overall_accesses          597942477                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_avg_miss_latency  3518.594842                       # average overall miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency  2810.845677                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0>                       # average overall mshr uncacheable latency
+system.cpu.dcache.overall_hits              595324251                       # number of overall hits
+system.cpu.dcache.overall_miss_latency     9212476500                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_rate          0.004379                       # miss rate for overall accesses
+system.cpu.dcache.overall_misses              2618226                       # number of overall misses
+system.cpu.dcache.overall_mshr_hits           2115150                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_miss_latency   1414069000                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_rate     0.000841                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_misses          503076                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
+system.cpu.dcache.prefetcher.num_hwpf_already_in_cache            0                       # number of hwpf that were already in the cache
+system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr            0                       # number of hwpf that were already in mshr
+system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher            0                       # number of hwpf that were already in the prefetch queue
+system.cpu.dcache.prefetcher.num_hwpf_evicted            0                       # number of hwpf removed due to no buffer left
+system.cpu.dcache.prefetcher.num_hwpf_identified            0                       # number of hwpf identified
+system.cpu.dcache.prefetcher.num_hwpf_issued            0                       # number of hwpf issued
+system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit            0                       # number of hwpf removed because MSHR allocated
+system.cpu.dcache.prefetcher.num_hwpf_span_page            0                       # number of hwpf spanning a virtual page
+system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss            0                       # number of hwpf that got squashed due to a miss aborting calculation time
+system.cpu.dcache.replacements                 498987                       # number of replacements
+system.cpu.dcache.sampled_refs                 503083                       # Sample count of references to valid blocks.
+system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.dcache.tagsinuse               4095.797134                       # Cycle average of tags in use
+system.cpu.dcache.total_refs                595325570                       # Total number of references to valid blocks.
+system.cpu.dcache.warmup_cycle               77974000                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.writebacks                   335737                       # number of writebacks
+system.cpu.decode.DECODE:BlockedCycles      435745843                       # Number of cycles decode is blocked
+system.cpu.decode.DECODE:DecodedInsts      3276032607                       # Number of instructions handled by decode
+system.cpu.decode.DECODE:IdleCycles        1073744654                       # Number of cycles decode is idle
+system.cpu.decode.DECODE:RunCycles          761619600                       # Number of cycles decode is running
+system.cpu.decode.DECODE:SquashCycles       241293837                       # Number of cycles decode is squashing
+system.cpu.decode.DECODE:UnblockCycles        2367171                       # Number of cycles decode is unblocking
+system.cpu.fetch.Branches                   223339092                       # Number of branches that fetch encountered
+system.cpu.fetch.CacheLines                 355860305                       # Number of cache lines fetched
+system.cpu.fetch.Cycles                    1166695920                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.IcacheSquashes              14770227                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.Insts                     3591774268                       # Number of instructions fetch has processed
+system.cpu.fetch.SquashCycles                93734364                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.branchRate                  0.088811                       # Number of branch fetches per cycle
+system.cpu.fetch.icacheStallCycles          355860305                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.predictedBranches          155497873                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.rate                        1.428271                       # Number of inst fetches per cycle
+system.cpu.fetch.rateDist.start_dist                           # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist.samples          2514771105                      
+system.cpu.fetch.rateDist.min_value                 0                      
+                               0   1703935491   6775.71%           
+                               1    252157679   1002.71%           
+                               2     75632424    300.75%           
+                               3     38096592    151.49%           
+                               4     76680653    304.92%           
+                               5     30840750    122.64%           
+                               6     33076966    131.53%           
+                               7     20130593     80.05%           
+                               8    284219957   1130.20%           
+system.cpu.fetch.rateDist.max_value                 8                      
+system.cpu.fetch.rateDist.end_dist
+
+system.cpu.icache.ReadReq_accesses          355860305                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_avg_miss_latency  5111.111111                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency  4198.640483                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_hits              355858946                       # number of ReadReq hits
+system.cpu.icache.ReadReq_miss_latency        6946000                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_rate          0.000004                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_misses                 1359                       # number of ReadReq misses
+system.cpu.icache.ReadReq_mshr_hits                35                       # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_miss_latency      5559000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate     0.000004                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_misses            1324                       # number of ReadReq MSHR misses
+system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0>                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0>                       # average number of cycles each access was blocked
+system.cpu.icache.avg_refs               268775.638973                       # Average number of references to valid blocks.
+system.cpu.icache.blocked_no_mshrs                  0                       # number of cycles access was blocked
+system.cpu.icache.blocked_no_targets                0                       # number of cycles access was blocked
+system.cpu.icache.blocked_cycles_no_mshrs            0                       # number of cycles access was blocked
+system.cpu.icache.blocked_cycles_no_targets            0                       # number of cycles access was blocked
+system.cpu.icache.cache_copies                      0                       # number of cache copies performed
+system.cpu.icache.demand_accesses           355860305                       # number of demand (read+write) accesses
+system.cpu.icache.demand_avg_miss_latency  5111.111111                       # average overall miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency  4198.640483                       # average overall mshr miss latency
+system.cpu.icache.demand_hits               355858946                       # number of demand (read+write) hits
+system.cpu.icache.demand_miss_latency         6946000                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_rate           0.000004                       # miss rate for demand accesses
+system.cpu.icache.demand_misses                  1359                       # number of demand (read+write) misses
+system.cpu.icache.demand_mshr_hits                 35                       # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_miss_latency      5559000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_rate      0.000004                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_misses             1324                       # number of demand (read+write) MSHR misses
+system.cpu.icache.fast_writes                       0                       # number of fast writes performed
+system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
+system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
+system.cpu.icache.overall_accesses          355860305                       # number of overall (read+write) accesses
+system.cpu.icache.overall_avg_miss_latency  5111.111111                       # average overall miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency  4198.640483                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0>                       # average overall mshr uncacheable latency
+system.cpu.icache.overall_hits              355858946                       # number of overall hits
+system.cpu.icache.overall_miss_latency        6946000                       # number of overall miss cycles
+system.cpu.icache.overall_miss_rate          0.000004                       # miss rate for overall accesses
+system.cpu.icache.overall_misses                 1359                       # number of overall misses
+system.cpu.icache.overall_mshr_hits                35                       # number of overall MSHR hits
+system.cpu.icache.overall_mshr_miss_latency      5559000                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_rate     0.000004                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_misses            1324                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
+system.cpu.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
+system.cpu.icache.prefetcher.num_hwpf_already_in_cache            0                       # number of hwpf that were already in the cache
+system.cpu.icache.prefetcher.num_hwpf_already_in_mshr            0                       # number of hwpf that were already in mshr
+system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher            0                       # number of hwpf that were already in the prefetch queue
+system.cpu.icache.prefetcher.num_hwpf_evicted            0                       # number of hwpf removed due to no buffer left
+system.cpu.icache.prefetcher.num_hwpf_identified            0                       # number of hwpf identified
+system.cpu.icache.prefetcher.num_hwpf_issued            0                       # number of hwpf issued
+system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit            0                       # number of hwpf removed because MSHR allocated
+system.cpu.icache.prefetcher.num_hwpf_span_page            0                       # number of hwpf spanning a virtual page
+system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss            0                       # number of hwpf that got squashed due to a miss aborting calculation time
+system.cpu.icache.replacements                    198                       # number of replacements
+system.cpu.icache.sampled_refs                   1324                       # Sample count of references to valid blocks.
+system.cpu.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.icache.tagsinuse               1026.431065                       # Cycle average of tags in use
+system.cpu.icache.total_refs                355858946                       # Total number of references to valid blocks.
+system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
+system.cpu.icache.writebacks                        0                       # number of writebacks
+system.cpu.idleCycles                            1497                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.iew.EXEC:branches                128998684                       # Number of branches executed
+system.cpu.iew.EXEC:nop                             0                       # number of nop insts executed
+system.cpu.iew.EXEC:rate                     0.879999                       # Inst execution rate
+system.cpu.iew.EXEC:refs                    756340485                       # number of memory reference insts executed
+system.cpu.iew.EXEC:stores                  208683785                       # Number of stores executed
+system.cpu.iew.EXEC:swp                             0                       # number of swp insts executed
+system.cpu.iew.WB:consumers                1511846593                       # num instructions consuming a value
+system.cpu.iew.WB:count                    2184193190                       # cumulative count of insts written-back
+system.cpu.iew.WB:fanout                     0.964010                       # average fanout of values written-back
+system.cpu.iew.WB:penalized                         0                       # number of instrctions required to write to 'other' IQ
+system.cpu.iew.WB:penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
+system.cpu.iew.WB:producers                1457435157                       # num instructions producing a value
+system.cpu.iew.WB:rate                       0.868546                       # insts written-back per cycle
+system.cpu.iew.WB:sent                     2194556483                       # cumulative count of insts sent to commit
+system.cpu.iew.branchMispredicts             93921260                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewBlockCycles                  242324                       # Number of cycles IEW is blocking
+system.cpu.iew.iewDispLoadInsts             751805606                       # Number of dispatched load instructions
+system.cpu.iew.iewDispNonSpecInsts           21112863                       # Number of dispatched non-speculative instructions
+system.cpu.iew.iewDispSquashedInsts           6967923                       # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispStoreInsts            305482201                       # Number of dispatched store instructions
+system.cpu.iew.iewDispatchedInsts          2889028359                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewExecLoadInsts             547656700                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts         155922171                       # Number of squashed instructions skipped in execute
+system.cpu.iew.iewExecutedInsts            2212995141                       # Number of executed instructions
+system.cpu.iew.iewIQFullEvents                      0                       # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
+system.cpu.iew.iewLSQFullEvents                     0                       # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.iewSquashCycles              241293837                       # Number of cycles IEW is squashing
+system.cpu.iew.iewUnblockCycles                  1173                       # Number of cycles IEW is unblocking
+system.cpu.iew.lsq.thread.0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
+system.cpu.iew.lsq.thread.0.cacheBlocked            0                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread.0.forwLoads       116560202                       # Number of loads that had data forwarded from stores
+system.cpu.iew.lsq.thread.0.ignoredResponses       586068                       # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread.0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
+system.cpu.iew.lsq.thread.0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
+system.cpu.iew.lsq.thread.0.memOrderViolation      3827981                       # Number of memory ordering violations
+system.cpu.iew.lsq.thread.0.rescheduledLoads           59                       # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread.0.squashedLoads    349293917                       # Number of loads squashed
+system.cpu.iew.lsq.thread.0.squashedStores    138634233                       # Number of stores squashed
+system.cpu.iew.memOrderViolationEvents        3827981                       # Number of memory order violations
+system.cpu.iew.predictedNotTakenIncorrect      1127857                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.predictedTakenIncorrect       92793403                       # Number of branches that were predicted taken incorrectly
+system.cpu.ipc                               0.592306                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         0.592306                       # IPC: Total IPC of All Threads
+system.cpu.iq.ISSUE:FU_type_0              2368917312                       # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0.start_dist
+                      No_OpClass    351375247     14.83%            # Type of FU issued
+                          IntAlu   1188705257     50.18%            # Type of FU issued
+                         IntMult            0      0.00%            # Type of FU issued
+                          IntDiv            0      0.00%            # Type of FU issued
+                        FloatAdd      2951238      0.12%            # Type of FU issued
+                        FloatCmp            0      0.00%            # Type of FU issued
+                        FloatCvt            0      0.00%            # Type of FU issued
+                       FloatMult            0      0.00%            # Type of FU issued
+                        FloatDiv            0      0.00%            # Type of FU issued
+                       FloatSqrt            0      0.00%            # Type of FU issued
+                         MemRead    592531661     25.01%            # Type of FU issued
+                        MemWrite    233353909      9.85%            # Type of FU issued
+                       IprAccess            0      0.00%            # Type of FU issued
+                    InstPrefetch            0      0.00%            # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0.end_dist
+system.cpu.iq.ISSUE:fu_busy_cnt               6622922                       # FU busy when requested
+system.cpu.iq.ISSUE:fu_busy_rate             0.002796                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.ISSUE:fu_full.start_dist
+                      No_OpClass            0      0.00%            # attempts to use FU when none available
+                          IntAlu      3150287     47.57%            # attempts to use FU when none available
+                         IntMult            0      0.00%            # attempts to use FU when none available
+                          IntDiv            0      0.00%            # attempts to use FU when none available
+                        FloatAdd       202242      3.05%            # attempts to use FU when none available
+                        FloatCmp            0      0.00%            # attempts to use FU when none available
+                        FloatCvt            0      0.00%            # attempts to use FU when none available
+                       FloatMult            0      0.00%            # attempts to use FU when none available
+                        FloatDiv            0      0.00%            # attempts to use FU when none available
+                       FloatSqrt            0      0.00%            # attempts to use FU when none available
+                         MemRead      2975364     44.93%            # attempts to use FU when none available
+                        MemWrite       295029      4.45%            # attempts to use FU when none available
+                       IprAccess            0      0.00%            # attempts to use FU when none available
+                    InstPrefetch            0      0.00%            # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full.end_dist
+system.cpu.iq.ISSUE:issued_per_cycle.start_dist                     # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle.samples   2514771105                      
+system.cpu.iq.ISSUE:issued_per_cycle.min_value            0                      
+                               0   1264571415   5028.57%           
+                               1    618163663   2458.13%           
+                               2    318214573   1265.38%           
+                               3    195947630    779.19%           
+                               4     78232851    311.09%           
+                               5     28085074    111.68%           
+                               6      8167595     32.48%           
+                               7      2987163     11.88%           
+                               8       401141      1.60%           
+system.cpu.iq.ISSUE:issued_per_cycle.max_value            8                      
+system.cpu.iq.ISSUE:issued_per_cycle.end_dist
+
+system.cpu.iq.ISSUE:rate                     0.942001                       # Inst issue rate
+system.cpu.iq.iqInstsAdded                 2867645475                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqInstsIssued                2368917312                       # Number of instructions issued
+system.cpu.iq.iqNonSpecInstsAdded            21382884                       # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqSquashedInstsExamined      1368214032                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedInstsIssued            461256                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedNonSpecRemoved       19139385                       # Number of squashed non-spec instructions that were removed
+system.cpu.iq.iqSquashedOperandsExamined   1296493196                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.l2cache.ReadReq_accesses            504406                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_avg_miss_latency  4393.799833                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency  2267.430007                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_hits                476939                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_miss_latency     120684500                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_rate         0.054454                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_misses               27467                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency     62279500                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate     0.054454                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_misses          27467                       # number of ReadReq MSHR misses
+system.cpu.l2cache.Writeback_accesses          335737                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_hits              335720                       # number of Writeback hits
+system.cpu.l2cache.Writeback_miss_rate       0.000051                       # miss rate for Writeback accesses
+system.cpu.l2cache.Writeback_misses                17                       # number of Writeback misses
+system.cpu.l2cache.Writeback_mshr_miss_rate     0.000051                       # mshr miss rate for Writeback accesses
+system.cpu.l2cache.Writeback_mshr_misses           17                       # number of Writeback MSHR misses
+system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0>                       # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0>                       # average number of cycles each access was blocked
+system.cpu.l2cache.avg_refs                 29.586740                       # Average number of references to valid blocks.
+system.cpu.l2cache.blocked_no_mshrs                 0                       # number of cycles access was blocked
+system.cpu.l2cache.blocked_no_targets               0                       # number of cycles access was blocked
+system.cpu.l2cache.blocked_cycles_no_mshrs            0                       # number of cycles access was blocked
+system.cpu.l2cache.blocked_cycles_no_targets            0                       # number of cycles access was blocked
+system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
+system.cpu.l2cache.demand_accesses             504406                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_avg_miss_latency  4393.799833                       # average overall miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency  2267.430007                       # average overall mshr miss latency
+system.cpu.l2cache.demand_hits                 476939                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_miss_latency      120684500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_rate          0.054454                       # miss rate for demand accesses
+system.cpu.l2cache.demand_misses                27467                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_mshr_hits                 0                       # number of demand (read+write) MSHR hits
+system.cpu.l2cache.demand_mshr_miss_latency     62279500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_rate     0.054454                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_misses           27467                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
+system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
+system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
+system.cpu.l2cache.overall_accesses            840143                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_avg_miss_latency  4391.082084                       # average overall miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency  2267.430007                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0>                       # average overall mshr uncacheable latency
+system.cpu.l2cache.overall_hits                812659                       # number of overall hits
+system.cpu.l2cache.overall_miss_latency     120684500                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_rate         0.032713                       # miss rate for overall accesses
+system.cpu.l2cache.overall_misses               27484                       # number of overall misses
+system.cpu.l2cache.overall_mshr_hits                0                       # number of overall MSHR hits
+system.cpu.l2cache.overall_mshr_miss_latency     62279500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_rate     0.032693                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_misses          27467                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
+system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache            0                       # number of hwpf that were already in the cache
+system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr            0                       # number of hwpf that were already in mshr
+system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher            0                       # number of hwpf that were already in the prefetch queue
+system.cpu.l2cache.prefetcher.num_hwpf_evicted            0                       # number of hwpf removed due to no buffer left
+system.cpu.l2cache.prefetcher.num_hwpf_identified            0                       # number of hwpf identified
+system.cpu.l2cache.prefetcher.num_hwpf_issued            0                       # number of hwpf issued
+system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit            0                       # number of hwpf removed because MSHR allocated
+system.cpu.l2cache.prefetcher.num_hwpf_span_page            0                       # number of hwpf spanning a virtual page
+system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss            0                       # number of hwpf that got squashed due to a miss aborting calculation time
+system.cpu.l2cache.replacements                  2692                       # number of replacements
+system.cpu.l2cache.sampled_refs                 27467                       # Sample count of references to valid blocks.
+system.cpu.l2cache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.l2cache.tagsinuse             24466.224839                       # Cycle average of tags in use
+system.cpu.l2cache.total_refs                  812659                       # Total number of references to valid blocks.
+system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.writebacks                    2555                       # number of writebacks
+system.cpu.numCycles                       2514771105                       # number of cpu cycles simulated
+system.cpu.rename.RENAME:BlockCycles         14153952                       # Number of cycles rename is blocking
+system.cpu.rename.RENAME:CommittedMaps     1244762263                       # Number of HB maps that are committed
+system.cpu.rename.RENAME:IQFullEvents             845                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.RENAME:IdleCycles        1122858502                       # Number of cycles rename is idle
+system.cpu.rename.RENAME:LSQFullEvents       18964355                       # Number of times rename has blocked due to LSQ full
+system.cpu.rename.RENAME:RenameLookups     4974059876                       # Number of register rename lookups that rename has made
+system.cpu.rename.RENAME:RenamedInsts      3105364972                       # Number of instructions processed by rename
+system.cpu.rename.RENAME:RenamedOperands   2435580679                       # Number of destination operands rename has renamed
+system.cpu.rename.RENAME:RunCycles          713636177                       # Number of cycles rename is running
+system.cpu.rename.RENAME:SquashCycles       241293837                       # Number of cycles rename is squashing
+system.cpu.rename.RENAME:UnblockCycles       24303898                       # Number of cycles rename is unblocking
+system.cpu.rename.RENAME:UndoneMaps        1190818416                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.RENAME:serializeStallCycles    398524739                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RENAME:serializingInsts     21495577                       # count of serializing insts renamed
+system.cpu.rename.RENAME:skidInsts          149561373                       # count of insts added to the skid buffer
+system.cpu.rename.RENAME:tempSerializingInsts     21338548                       # count of temporary serializing insts renamed
+system.cpu.timesIdled                               3                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.workload.PROG:num_syscalls              19                       # Number of system calls
+
+---------- End Simulation Statistics   ----------